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Update I2C module documentation (#3000)
* feat: Avoid raw md link * docs: Improve i2c master docs * fix: Typo Co-authored-by: Juraj Sadel <jurajsadel@gmail.com> --------- Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
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//! # Inter-Integrated Circuit (I2C) - Master mode
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//!
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//! ## Overview
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//!
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//! In this mode, the I2C acts as master and initiates the I2C communication by
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//! generating a START condition. Note that only one master is allowed to occupy
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//! the bus to access one slave at the same time.
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//!
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//! ## Configuration
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//!
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//! Each I2C controller is individually configurable, and the usual setting
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//! such as frequency, timeout, and SDA/SCL pins can easily be configured.
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//! Each I2C Master controller is individually configurable, and the usual
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//! setting such as frequency, timeout, and SDA/SCL pins can easily be
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//! configured.
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//!
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//! ## Usage
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//!
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//! }
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//! # }
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//! ```
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//! [`embedded-hal`]: https://docs.rs/embedded-hal/latest/embedded_hal/index.html
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//!
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//! [`embedded-hal`]:embedded_hal
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use core::marker::PhantomData;
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#[cfg(not(esp32))]
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//! protocol that allows co-existence of multiple masters and slaves on the
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//! same bus. I2C uses two bidirectional open-drain lines: serial data line
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//! (SDA) and serial clock line (SCL), pulled up by resistors.
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//!
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//! For more information, see
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#![doc = crate::trm_markdown_link!("i2c")]
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pub mod master;
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