Configurable LP Core clock (#907)

* Configurable LP Core clock

* CHANGELOG.md entry

CHANGELOG.md

@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## [Unreleased]
 
 ### Added
+- ESP32-C6: LP core clock is configurable (#907)
 
 ### Changed
 

esp-hal-common/src/soc/esp32c6/lp_core.rs

@@ -68,20 +68,56 @@ pub enum LpCoreWakeupSource {
     HpCpu,
 }
 
+/// Clock sources for the LP core
+#[derive(Debug, Clone, Copy)]
+pub enum LpCoreClockSource {
+    /// 17.5 MHz clock
+    ///
+    /// Might not be very accurate
+    RcFastClk,
+    /// 20 MHz clock
+    XtalD2Clk,
+}
+
 pub struct LpCore<'d> {
     _lp_core: PeripheralRef<'d, crate::soc::peripherals::LP_CORE>,
 }
 
 impl<'d> LpCore<'d> {
+    /// Create a new instance using [LpCoreClockSource::RcFastClk]
     pub fn new(lp_core: impl Peripheral<P = crate::soc::peripherals::LP_CORE> + 'd) -> Self {
+        LpCore::new_with_clock(lp_core, LpCoreClockSource::RcFastClk)
+    }
+
+    /// Create a new instance using the given clock
+    pub fn new_with_clock(
+        lp_core: impl Peripheral<P = crate::soc::peripherals::LP_CORE> + 'd,
+        clk_src: LpCoreClockSource,
+    ) -> Self {
         crate::into_ref!(lp_core);
+
+        match clk_src {
+            LpCoreClockSource::RcFastClk => unsafe {
+                (&*crate::soc::peripherals::LP_CLKRST::PTR)
+                    .lp_clk_conf
+                    .modify(|_, w| w.fast_clk_sel().clear_bit())
+            },
+            LpCoreClockSource::XtalD2Clk => unsafe {
+                (&*crate::soc::peripherals::LP_CLKRST::PTR)
+                    .lp_clk_conf
+                    .modify(|_, w| w.fast_clk_sel().set_bit())
+            },
+        }
+
         Self { _lp_core: lp_core }
     }
 
+    /// Stop the LP core
     pub fn stop(&mut self) {
         ulp_lp_core_stop();
     }
 
+    /// Start the LP core
     pub fn run(&mut self, wakeup_src: LpCoreWakeupSource) {
         ulp_lp_core_run(wakeup_src);
     }

esp32c6-lp-hal/src/delay.rs

@@ -14,7 +14,7 @@ pub struct Delay {
 impl Delay {
     pub fn new() -> Self {
         Self {
-            rv_delay: riscv::delay::McycleDelay::new(CPU_CLOCK),
+            rv_delay: riscv::delay::McycleDelay::new(unsafe { CPU_CLOCK }),
         }
     }
 }

esp32c6-lp-hal/src/lib.rs

@@ -14,7 +14,11 @@ pub mod riscv {
 }
 pub mod prelude;
 
-const CPU_CLOCK: u32 = 16_000_000;
+// LP_FAST_CLK is not very accurate, for now use a rough estimate
+const LP_FAST_CLK_HZ: u32 = 16_000_000;
+const XTAL_D2_CLK_HZ: u32 = 20_000_000;
+
+pub static mut CPU_CLOCK: u32 = LP_FAST_CLK_HZ;
 
 global_asm!(
     r#"
@@ -60,6 +64,11 @@ unsafe extern "C" fn lp_core_startup() -> ! {
         fn main() -> !;
     }
 
+    let clkrst = &*esp32c6_lp::LP_CLKRST::PTR;
+    if clkrst.lp_clk_conf.read().fast_clk_sel().bit_is_set() {
+        CPU_CLOCK = XTAL_D2_CLK_HZ;
+    }
+
     main();
 }