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Remove direct boot support from esp-hal (#903)

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* Remove direct boot support from esp-hal

* changelog
This commit is contained in:
Scott Mabin 2023-11-07 14:34:46 +00:00 committed by GitHub
parent 780a7f5e4a
commit fb31f868f1
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GPG Key ID: 4AEE18F83AFDEB23
35 changed files with 9 additions and 1701 deletions
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16
.github/workflows/ci.yml vendored
View File

@ -131,8 +131,6 @@ jobs:
# for each supported image format.
- name: build esp32c2-hal (no features)
run: cd esp32c2-hal/ && cargo build --examples
- name: build esp32c2-hal (direct-boot)
run: cd esp32c2-hal/ && cargo build --examples --features=direct-boot
# Subsequent steps can just check the examples instead, as we're already
# confident that they link.
- name: check esp32c2-hal (common features)
@ -183,8 +181,6 @@ jobs:
# for each supported image format.
- name: build esp32c3-hal (no features)
run: cd esp32c3-hal/ && cargo +nightly build --examples
- name: build esp32c3-hal (direct-boot)
run: cd esp32c3-hal/ && cargo +nightly build --examples --features=direct-boot
- name: build esp32c3-hal (mcu-boot)
run: cd esp32c3-hal/ && cargo +nightly build --examples --features=mcu-boot
# Subsequent steps can just check the examples instead, as we're already
@ -242,8 +238,6 @@ jobs:
# for each supported image format.
- name: build esp32c6-hal (no features)
run: cd esp32c6-hal/ && cargo +nightly build --examples
- name: build esp32c6-hal (direct-boot)
run: cd esp32c6-hal/ && cargo +nightly build --examples --features=direct-boot
# Subsequent steps can just check the examples instead, as we're already
# confident that they link.
- name: check esp32c6-hal (common features)
@ -314,8 +308,6 @@ jobs:
# for each supported image format.
- name: build esp32h2-hal (no features)
run: cd esp32h2-hal/ && cargo +nightly build --examples
- name: build esp32h2-hal (direct-boot)
run: cd esp32h2-hal/ && cargo +nightly build --examples --features=direct-boot
# Subsequent steps can just check the examples instead, as we're already
# confident that they link.
- name: check esp32h2-hal (common features)
@ -382,7 +374,7 @@ jobs:
with:
target: riscv32imc-unknown-none-elf
toolchain: nightly
components: rust-src
components: rust-src
- uses: Swatinem/rust-cache@v2
# build the ulp-riscv-hal examples first to make sure the examples which expect
@ -457,7 +449,7 @@ jobs:
with:
target: riscv32imc-unknown-none-elf
toolchain: nightly
components: rust-src
components: rust-src
- uses: Swatinem/rust-cache@v2
# build the ulp-riscv-hal examples first to make sure the examples which expect
@ -471,8 +463,6 @@ jobs:
# for each supported image format.
- name: build esp32s3-hal (no features)
run: cd esp32s3-hal/ && cargo +esp build --examples
- name: build esp32s3-hal (direct-boot)
run: cd esp32s3-hal/ && cargo +esp build --examples --features=direct-boot
# Subsequent steps can just check the examples instead, as we're already
# confident that they link.
- name: check esp32s3-hal (common features)
@ -603,7 +593,7 @@ jobs:
with:
target: riscv32imc-unknown-none-elf
toolchain: "1.67"
components: rust-src
components: rust-src
- uses: Swatinem/rust-cache@v2
# build the ulp-riscv-hal examples first to make sure the examples which expect

4
CHANGELOG.md
View File

@ -21,6 +21,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
### Removed
### Breaking
- Direct boot support has been removed (#903).
## [0.13.1] - 2023-11-02
### Fixed

1
esp32c2-hal/Cargo.toml
View File

@ -54,7 +54,6 @@ default = ["rt", "vectored", "xtal-40mhz"]
async = ["esp-hal-common/async"]
debug = ["esp-hal-common/debug"]
defmt = ["esp-hal-common/defmt", "esp-println/defmt"]
direct-boot = ["esp-hal-common/rv-init-data"]
direct-vectoring = ["esp-hal-common/direct-vectoring"]
eh1 = ["esp-hal-common/eh1"]
interrupt-preemption = ["esp-hal-common/interrupt-preemption"]

26
esp32c2-hal/build.rs
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@ -1,31 +1,5 @@
use std::{env, error::Error, fs, path::PathBuf};
#[cfg(feature = "direct-boot")]
fn main() -> Result<(), Box<dyn Error>> {
check_features();
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out.display());
fs::copy("ld/db-esp32c2-memory.x", out.join("memory.x")).unwrap();
fs::copy("ld/db-esp32c2-link.x", out.join("esp32c2-link.x")).unwrap();
fs::copy("ld/db-riscv-link.x", out.join("riscv-link.x")).unwrap();
fs::copy("ld/db-linkall.x", out.join("linkall.x")).unwrap();
fs::copy("ld/rom-functions.x", out.join("rom-functions.x"))?;
// Only re-run the build script when memory.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=ld/memory.x");
#[cfg(feature = "defmt")]
println!("cargo:rustc-link-arg=-Tdefmt.x");
Ok(())
}
#[cfg(not(feature = "direct-boot"))]
fn main() -> Result<(), Box<dyn Error>> {
check_features();

14
esp32c2-hal/ld/db-esp32c2-link.x
View File

@ -1,14 +0,0 @@
INCLUDE memory.x
SECTIONS
{
.header : AT(0)
{
LONG(0xaedb041d)
LONG(0xaedb041d)
} > IROM
}
_stext = ORIGIN(IROM) + 8;
INCLUDE riscv-link.x

36
esp32c2-hal/ld/db-esp32c2-memory.x
View File

@ -1,36 +0,0 @@
MEMORY
{
/*
https://github.com/espressif/esptool/blob/10828527038d143e049790d330ac4de76ce987d6/esptool/targets/esp32c2.py#L53-L62
MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"],
[0x3C000000, 0x3C400000, "DROM"],
[0x3FCA0000, 0x3FCE0000, "DRAM"],
[0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
[0x3FF00000, 0x3FF50000, "DROM_MASK"],
[0x40000000, 0x40090000, "IROM_MASK"],
[0x42000000, 0x42400000, "IROM"],
[0x4037C000, 0x403C0000, "IRAM"]]
*/
/* 272K of on soc RAM, 16K reserved for cache */
ICACHE : ORIGIN = 0x4037C000, LENGTH = 16K
/* Instruction RAM */
IRAM : ORIGIN = 0x4037C000 + 16K, LENGTH = 272K - 16K
/* Data RAM */
DRAM : ORIGIN = 0x3FCA0000, LENGTH = 0x30000
/* External flash */
/* Instruction ROM */
IROM : ORIGIN = 0x42000000, LENGTH = 0x200000
/* Data ROM */
DROM : ORIGIN = 0x3C000000, LENGTH = 0x200000
}
REGION_ALIAS("REGION_TEXT", IROM);
REGION_ALIAS("REGION_RODATA", DROM);
REGION_ALIAS("REGION_DATA", DRAM);
REGION_ALIAS("REGION_BSS", DRAM);
REGION_ALIAS("REGION_STACK", DRAM);
REGION_ALIAS("REGION_RWTEXT", IRAM);

3
esp32c2-hal/ld/db-linkall.x
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@ -1,3 +0,0 @@
INCLUDE "esp32c2-link.x"
INCLUDE "hal-defaults.x"
INCLUDE "rom-functions.x"

177
esp32c2-hal/ld/db-riscv-link.x
View File

@ -1,177 +0,0 @@
ENTRY(_start)
PROVIDE(_stext = ORIGIN(REGION_TEXT));
PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
PROVIDE(_max_hart_id = 0);
PROVIDE(UserSoft = DefaultHandler);
PROVIDE(SupervisorSoft = DefaultHandler);
PROVIDE(MachineSoft = DefaultHandler);
PROVIDE(UserTimer = DefaultHandler);
PROVIDE(SupervisorTimer = DefaultHandler);
PROVIDE(MachineTimer = DefaultHandler);
PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler);
PROVIDE(__post_init = default_post_init);
/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
PROVIDE(_setup_interrupts = default_setup_interrupts);
/* # Multi-processing hook function
fn _mp_hook() -> bool;
This function is called from all the harts and must return true only for one hart,
which will perform memory initialization. For other harts it must return false
and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
*/
PROVIDE(_mp_hook = default_mp_hook);
/* # Start trap function override
By default uses the riscv crates default trap handler
but by providing the `_start_trap` symbol external crates can override.
*/
PROVIDE(_start_trap = default_start_trap);
SECTIONS
{
.text.dummy (NOLOAD) :
{
/* This section is intended to make _stext address work */
. = ABSOLUTE(_stext);
} > REGION_TEXT
.text _stext :
{
/* Put reset handler first in .text section so it ends up as the entry */
/* point of the program. */
KEEP(*(.init));
KEEP(*(.init.rust));
KEEP(*(.text.abort));
. = ALIGN(4);
*(.text .text.*);
_etext = .;
} > REGION_TEXT
_text_size = _etext - _stext + 8;
.rodata ORIGIN(DROM) + _text_size : AT(_text_size)
{
_srodata = .;
*(.srodata .srodata.*);
*(.rodata .rodata.*);
/* 4-byte align the end (VMA) of this section.
This is required by LLD to ensure the LMA of the following .data
section will have the correct alignment. */
. = ALIGN(4);
_erodata = .;
} > REGION_RODATA
_rodata_size = _erodata - _srodata + 8;
.data ORIGIN(DRAM) : AT(_text_size + _rodata_size)
{
_data_start = .;
/* Must be called __global_pointer$ for linker relaxations to work. */
PROVIDE(__global_pointer$ = . + 0x800);
*(.sdata .sdata.* .sdata2 .sdata2.*);
*(.data .data.*);
. = ALIGN(4);
_data_end = .;
} > REGION_DATA
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;
.rwtext.dummy (NOLOAD):
{
/* This section is required to skip .rwtext area because REGION_RWTEXT
* and REGION_BSS reflect the same address space on different buses.
*/
. = ORIGIN(REGION_DATA) + _rwtext_size + 8 + SIZEOF(.data);
} > REGION_DATA
.bss (NOLOAD) :
{
_bss_start = .;
*(.sbss .sbss.* .bss .bss.*);
. = ALIGN(4);
_bss_end = .;
} > REGION_BSS
/* fictitious region that represents the memory available for the stack */
.stack (NOLOAD) :
{
_estack = .;
. = ABSOLUTE(_stack_start);
_sstack = .;
} > REGION_STACK
/* fake output .got section */
/* Dynamic relocations are unsupported. This section is only used to detect
relocatable code in the input files and raise an error if relocatable code
is found */
.got (INFO) :
{
KEEP(*(.got .got.*));
}
.eh_frame (INFO) : { KEEP(*(.eh_frame)) }
.eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
}
PROVIDE(_sidata = _erodata + 8);
PROVIDE(_irwtext = ORIGIN(DROM) + _text_size + _rodata_size + _data_size);
/* Do not exceed this mark in the error messages above | */
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
ASSERT(_stext % 4 == 0, "
ERROR(riscv-rt): `_stext` must be 4-byte aligned");
ASSERT(_data_start % 4 == 0 && _data_end % 4 == 0, "
BUG(riscv-rt): .data is not 4-byte aligned");
ASSERT(_sidata % 4 == 0, "
BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
ASSERT(_bss_start % 4 == 0 && _bss_end % 4 == 0, "
BUG(riscv-rt): .bss is not 4-byte aligned");
ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
ASSERT(SIZEOF(.got) == 0, "
.got section detected in the input files. Dynamic relocations are not
supported. If you are linking to C code compiled using the `gcc` crate
then modify your build script to compile the C code _without_ the
-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
details.");
/* Do not exceed this mark in the error messages above | */

11
esp32c2-hal/src/lib.rs
View File

@ -11,7 +11,6 @@
//! provided by [embedded-hal-async] and [embedded-io-async]
//! - `debug` - Enable debug features in the HAL (used for development)
//! - `defmt` - Enable [`defmt::Format`] on certain types
//! - `direct-boot` - Use the direct boot image format
//! - `direct-vectoring` - Enable direct vector table hooking support
//! - `eh1` - Implement the traits defined in the `1.0.0-xxx` pre-releases of
//! [embedded-hal], [embedded-hal-nb], and [embedded-io]
@ -60,16 +59,6 @@
//!
//! [ESP-IDF]: https://github.com/espressif/esp-idf
//! [App Image Format]: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/app_image_format.html
//!
//! #### Direct Boot
//!
//! This device additionally supports direct-boot, which allows an application
//! to be executed directly from flash, without using the second-stage
//! bootloader. For more information please see the
//! [esp32c3-direct-boot-example] in the Espressif organization on GitHub.
//!
//! [esp32c3-direct-boot-example]: https://github.com/espressif/esp32c3-direct-boot-example
#![no_std]
#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]

1
esp32c3-hal/Cargo.toml
View File

@ -57,7 +57,6 @@ default = ["rt", "vectored", "esp-hal-common/rv-zero-rtc-bss"]
async = ["esp-hal-common/async"]
debug = ["esp-hal-common/debug"]
defmt = ["esp-hal-common/defmt", "esp-println/defmt"]
direct-boot = ["esp-hal-common/rv-init-data", "esp-hal-common/rv-init-rtc-data"]
direct-vectoring = ["esp-hal-common/direct-vectoring"]
eh1 = ["esp-hal-common/eh1"]
interrupt-preemption = ["esp-hal-common/interrupt-preemption"]

40
esp32c3-hal/build.rs
View File

@ -1,21 +1,6 @@
use std::{env, error::Error, fs, path::PathBuf};
// Given some features, assert that AT MOST one of the features is enabled.
macro_rules! assert_unique_features {
() => {};
( $first:tt $(,$rest:tt)* ) => {
$(
#[cfg(all(feature = $first, feature = $rest))]
compile_error!(concat!("Features \"", $first, "\" and \"", $rest, "\" cannot be used together"));
)*
assert_unique_features!($($rest),*);
};
}
assert_unique_features! {"direct-boot", "mcu-boot"}
#[cfg(not(any(feature = "direct-boot", feature = "mcu-boot")))]
#[cfg(not(feature = "mcu-boot"))]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
@ -37,29 +22,6 @@ fn main() -> Result<(), Box<dyn Error>> {
Ok(())
}
#[cfg(feature = "direct-boot")]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out.display());
fs::copy("ld/db-esp32c3-memory.x", out.join("memory.x"))?;
fs::copy("ld/db-esp32c3-link.x", out.join("esp32c3-link.x"))?;
fs::copy("ld/db-riscv-link.x", out.join("riscv-link.x"))?;
fs::copy("ld/db-linkall.x", out.join("linkall.x"))?;
fs::copy("ld/rom-functions.x", out.join("rom-functions.x"))?;
// Only re-run the build script when memory.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=ld/memory.x");
#[cfg(feature = "defmt")]
println!("cargo:rustc-link-arg=-Tdefmt.x");
Ok(())
}
#[cfg(feature = "mcu-boot")]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it

14
esp32c3-hal/ld/db-esp32c3-link.x
View File

@ -1,14 +0,0 @@
INCLUDE memory.x
SECTIONS
{
.header : AT(0)
{
LONG(0xaedb041d)
LONG(0xaedb041d)
} > IROM
}
_stext = ORIGIN(IROM) + 8;
INCLUDE riscv-link.x

43
esp32c3-hal/ld/db-esp32c3-memory.x
View File

@ -1,43 +0,0 @@
MEMORY
{
/*
https://github.com/espressif/esptool/blob/ed64d20b051d05f3f522bacc6a786098b562d4b8/esptool/targets/esp32c3.py#L78-L90
MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"],
[0x3C000000, 0x3C800000, "DROM"],
[0x3FC80000, 0x3FCE0000, "DRAM"],
[0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
[0x3FF00000, 0x3FF20000, "DROM_MASK"],
[0x40000000, 0x40060000, "IROM_MASK"],
[0x42000000, 0x42800000, "IROM"],
[0x4037C000, 0x403E0000, "IRAM"],
[0x50000000, 0x50002000, "RTC_IRAM"],
[0x50000000, 0x50002000, "RTC_DRAM"],
[0x600FE000, 0x60100000, "MEM_INTERNAL2"]]
*/
/* 400K of on soc RAM, 16K reserved for cache */
ICACHE : ORIGIN = 0x4037C000, LENGTH = 0x4000
/* Instruction RAM */
IRAM : ORIGIN = 0x4037C000 + 0x4000, LENGTH = 400K - 0x4000
/* Data RAM */
DRAM : ORIGIN = 0x3FC80000, LENGTH = 0x50000
/* External flash */
/* Instruction ROM */
IROM : ORIGIN = 0x42000000, LENGTH = 0x400000
/* Data ROM */
DROM : ORIGIN = 0x3C000000, LENGTH = 0x400000
/* RTC fast memory (executable). Persists over deep sleep. */
RTC_FAST : ORIGIN = 0x50000000, LENGTH = 0x2000 /*- ESP_BOOTLOADER_RESERVE_RTC*/
}
REGION_ALIAS("REGION_TEXT", IROM);
REGION_ALIAS("REGION_RODATA", DROM);
REGION_ALIAS("REGION_DATA", DRAM);
REGION_ALIAS("REGION_BSS", DRAM);
REGION_ALIAS("REGION_STACK", DRAM);
REGION_ALIAS("REGION_RWTEXT", IRAM);
REGION_ALIAS("REGION_RTC_FAST", RTC_FAST);

3
esp32c3-hal/ld/db-linkall.x
View File

@ -1,3 +0,0 @@
INCLUDE "esp32c3-link.x"
INCLUDE "hal-defaults.x"
INCLUDE "rom-functions.x"

219
esp32c3-hal/ld/db-riscv-link.x
View File

@ -1,219 +0,0 @@
ENTRY(_start)
PROVIDE(_stext = ORIGIN(REGION_TEXT));
PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
PROVIDE(_max_hart_id = 0);
PROVIDE(UserSoft = DefaultHandler);
PROVIDE(SupervisorSoft = DefaultHandler);
PROVIDE(MachineSoft = DefaultHandler);
PROVIDE(UserTimer = DefaultHandler);
PROVIDE(SupervisorTimer = DefaultHandler);
PROVIDE(MachineTimer = DefaultHandler);
PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler);
PROVIDE(__post_init = default_post_init);
/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
PROVIDE(_setup_interrupts = default_setup_interrupts);
/* # Multi-processing hook function
fn _mp_hook() -> bool;
This function is called from all the harts and must return true only for one hart,
which will perform memory initialization. For other harts it must return false
and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
*/
PROVIDE(_mp_hook = default_mp_hook);
/* # Start trap function override
By default uses the riscv crates default trap handler
but by providing the `_start_trap` symbol external crates can override.
*/
PROVIDE(_start_trap = default_start_trap);
SECTIONS
{
.text.dummy (NOLOAD) :
{
/* This section is intended to make _stext address work */
. = ABSOLUTE(_stext);
} > REGION_TEXT
.text _stext :
{
/* Put reset handler first in .text section so it ends up as the entry */
/* point of the program. */
KEEP(*(.init));
KEEP(*(.init.rust));
KEEP(*(.text.abort));
. = ALIGN(4);
*(.text .text.*);
_etext = .;
} > REGION_TEXT
_text_size = _etext - _stext + 8;
.rodata ORIGIN(DROM) + _text_size : AT(_text_size)
{
_srodata = .;
*(.srodata .srodata.*);
*(.rodata .rodata.*);
/* 4-byte align the end (VMA) of this section.
This is required by LLD to ensure the LMA of the following .data
section will have the correct alignment. */
. = ALIGN(4);
_erodata = .;
} > REGION_RODATA
_rodata_size = _erodata - _srodata + 8;
.data ORIGIN(DRAM) : AT(_text_size + _rodata_size)
{
_data_start = .;
/* Must be called __global_pointer$ for linker relaxations to work. */
PROVIDE(__global_pointer$ = . + 0x800);
*(.sdata .sdata.* .sdata2 .sdata2.*);
*(.data .data.*);
. = ALIGN(4);
_data_end = .;
} > REGION_DATA
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;
.rwtext.dummy (NOLOAD):
{
/* This section is required to skip .rwtext area because REGION_RWTEXT
* and REGION_BSS reflect the same address space on different buses.
*/
. = ORIGIN(REGION_DATA) + _rwtext_size + 8 + SIZEOF(.data);
} > REGION_DATA
.bss (NOLOAD) :
{
_bss_start = .;
*(.sbss .sbss.* .bss .bss.*);
. = ALIGN(4);
_bss_end = .;
} > REGION_BSS
/* ### .uninit */
.uninit (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
__suninit = .;
*(.uninit .uninit.*);
. = ALIGN(4);
__euninit = .;
} > REGION_BSS
/* fictitious region that represents the memory available for the stack */
.stack (NOLOAD) :
{
_estack = .;
. = ABSOLUTE(_stack_start);
_sstack = .;
} > REGION_STACK
.rtc_fast.text : AT(_text_size + _rodata_size + _data_size + _rwtext_size) {
_srtc_fast_text = .;
*(.rtc_fast.literal .rtc_fast.text .rtc_fast.literal.* .rtc_fast.text.*)
. = ALIGN(4);
_ertc_fast_text = .;
} > REGION_RTC_FAST
_fast_text_size = _ertc_fast_text - _srtc_fast_text + 8;
.rtc_fast.data : AT(_text_size + _rodata_size + _data_size + _rwtext_size + _fast_text_size)
{
_rtc_fast_data_start = ABSOLUTE(.);
*(.rtc_fast.data .rtc_fast.data.*)
. = ALIGN(4);
_rtc_fast_data_end = ABSOLUTE(.);
} > REGION_RTC_FAST
_rtc_fast_data_size = _rtc_fast_data_end - _rtc_fast_data_start + 8;
.rtc_fast.bss (NOLOAD) : ALIGN(4)
{
_rtc_fast_bss_start = ABSOLUTE(.);
*(.rtc_fast.bss .rtc_fast.bss.*)
. = ALIGN(4);
_rtc_fast_bss_end = ABSOLUTE(.);
} > REGION_RTC_FAST
.rtc_fast.noinit (NOLOAD) : ALIGN(4)
{
*(.rtc_fast.noinit .rtc_fast.noinit.*)
} > REGION_RTC_FAST
/* fake output .got section */
/* Dynamic relocations are unsupported. This section is only used to detect
relocatable code in the input files and raise an error if relocatable code
is found */
.got (INFO) :
{
KEEP(*(.got .got.*));
}
.eh_frame (INFO) : { KEEP(*(.eh_frame)) }
.eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
}
PROVIDE(_sidata = _erodata + 8);
PROVIDE(_irwtext = ORIGIN(DROM) + _text_size + _rodata_size + _data_size);
PROVIDE(_irtc_fast_text = ORIGIN(DROM) + _text_size + _rodata_size + _data_size + _rwtext_size);
PROVIDE(_irtc_fast_data = ORIGIN(DROM) + _text_size + _rodata_size + _data_size + _rwtext_size + _fast_text_size);
/* Do not exceed this mark in the error messages above | */
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
ASSERT(_stext % 4 == 0, "
ERROR(riscv-rt): `_stext` must be 4-byte aligned");
ASSERT(_data_start % 4 == 0 && _data_end % 4 == 0, "
BUG(riscv-rt): .data is not 4-byte aligned");
ASSERT(_sidata % 4 == 0, "
BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
ASSERT(_bss_start % 4 == 0 && _bss_end % 4 == 0, "
BUG(riscv-rt): .bss is not 4-byte aligned");
ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
ASSERT(SIZEOF(.got) == 0, "
.got section detected in the input files. Dynamic relocations are not
supported. If you are linking to C code compiled using the `gcc` crate
then modify your build script to compile the C code _without_ the
-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
details.");
/* Do not exceed this mark in the error messages above | */

10
esp32c3-hal/src/lib.rs
View File

@ -11,7 +11,6 @@
//! provided by [embedded-hal-async] and [embedded-io-async]
//! - `debug` - Enable debug features in the HAL (used for development)
//! - `defmt` - Enable [`defmt::Format`] on certain types
//! - `direct-boot` - Use the direct boot image format
//! - `direct-vectoring` - Enable direct vector table hooking support
//! - `eh1` - Implement the traits defined in the `1.0.0-xxx` pre-releases of
//! [embedded-hal], [embedded-hal-nb], and [embedded-io]
@ -60,15 +59,6 @@
//! [ESP-IDF]: https://github.com/espressif/esp-idf
//! [App Image Format]: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/app_image_format.html
//!
//! #### Direct Boot
//!
//! This device additionally supports direct-boot, which allows an application
//! to be executed directly from flash, without using the second-stage
//! bootloader. For more information please see the
//! [esp32c3-direct-boot-example] in the Espressif organization on GitHub.
//!
//! [esp32c3-direct-boot-example]: https://github.com/espressif/esp32c3-direct-boot-example
//!
//! #### MCUboot
//!
//! Use the MCUBoot bootloader and its associated image format. See the [MCUBoot

1
esp32c6-hal/Cargo.toml
View File

@ -60,7 +60,6 @@ default = ["rt", "vectored", "esp-hal-common/rv-zero-rtc-bss"]
async = ["esp-hal-common/async"]
debug = ["esp-hal-common/debug"]
defmt = ["esp-hal-common/defmt", "esp-println/defmt"]
direct-boot = ["esp-hal-common/rv-init-data", "esp-hal-common/rv-init-rtc-data"]
direct-vectoring = ["esp-hal-common/direct-vectoring"]
eh1 = ["esp-hal-common/eh1"]
interrupt-preemption = ["esp-hal-common/interrupt-preemption"]

24
esp32c6-hal/build.rs
View File

@ -1,6 +1,5 @@
use std::{env, error::Error, fs, path::PathBuf};
#[cfg(not(feature = "direct-boot"))]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
@ -21,26 +20,3 @@ fn main() -> Result<(), Box<dyn Error>> {
Ok(())
}
#[cfg(feature = "direct-boot")]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out.display());
fs::copy("ld/db-esp32c6-memory.x", out.join("memory.x"))?;
fs::copy("ld/db-esp32c6-link.x", out.join("esp32c6-link.x"))?;
fs::copy("ld/db-riscv-link.x", out.join("riscv-link.x"))?;
fs::copy("ld/db-linkall.x", out.join("linkall.x"))?;
fs::copy("ld/rom-functions.x", out.join("rom-functions.x"))?;
// Only re-run the build script when memory.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=ld/memory.x");
#[cfg(feature = "defmt")]
println!("cargo:rustc-link-arg=-Tdefmt.x");
Ok(())
}

14
esp32c6-hal/ld/db-esp32c6-link.x
View File

@ -1,14 +0,0 @@
INCLUDE memory.x
SECTIONS
{
.header : AT(0)
{
LONG(0xaedb041d)
LONG(0xaedb041d)
} > ROM
}
_stext = ORIGIN(ROM) + 8;
INCLUDE riscv-link.x

37
esp32c6-hal/ld/db-esp32c6-memory.x
View File

@ -1,37 +0,0 @@
MEMORY
{
/* MEMORY_MAP = [
[0x00000000, 0x00010000, "PADDING"],
[0x42800000, 0x43000000, "DROM"],
[0x40800000, 0x40880000, "DRAM"],
[0x40800000, 0x40880000, "BYTE_ACCESSIBLE"],
[0x4004AC00, 0x40050000, "DROM_MASK"],
[0x40000000, 0x4004AC00, "IROM_MASK"],
[0x42000000, 0x42800000, "IROM"],
[0x40800000, 0x40880000, "IRAM"],
[0x50000000, 0x50004000, "RTC_IRAM"],
[0x50000000, 0x50004000, "RTC_DRAM"],
[0x600FE000, 0x60100000, "MEM_INTERNAL2"],
] */
/* 512K of on soc RAM, 32K reserved for cache */
ICACHE : ORIGIN = 0x40800000, LENGTH = 32K
RAM : ORIGIN = 0x40800000 + 32K, LENGTH = 512K - 32K
/* External flash */
ROM : ORIGIN = 0x42000000, LENGTH = 0x400000
/* RTC fast memory (executable). Persists over deep sleep. */
RTC_FAST : ORIGIN = 0x50000000, LENGTH = 16K /*- ESP_BOOTLOADER_RESERVE_RTC*/
}
REGION_ALIAS("REGION_TEXT", ROM);
REGION_ALIAS("REGION_RODATA", ROM);
REGION_ALIAS("REGION_DATA", RAM);
REGION_ALIAS("REGION_BSS", RAM);
REGION_ALIAS("REGION_STACK", RAM);
REGION_ALIAS("REGION_RWTEXT", RAM);
REGION_ALIAS("REGION_RTC_FAST", RTC_FAST);

3
esp32c6-hal/ld/db-linkall.x
View File

@ -1,3 +0,0 @@
INCLUDE "esp32c6-link.x"
INCLUDE "hal-defaults.x"
INCLUDE "rom-functions.x"

216
esp32c6-hal/ld/db-riscv-link.x
View File

@ -1,216 +0,0 @@
ENTRY(_start)
PROVIDE(_stext = ORIGIN(REGION_TEXT));
PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
PROVIDE(_max_hart_id = 0);
PROVIDE(UserSoft = DefaultHandler);
PROVIDE(SupervisorSoft = DefaultHandler);
PROVIDE(MachineSoft = DefaultHandler);
PROVIDE(UserTimer = DefaultHandler);
PROVIDE(SupervisorTimer = DefaultHandler);
PROVIDE(MachineTimer = DefaultHandler);
PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler);
/* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6 has
IDs 0-31, so we much define the handler for the one additional interrupt
ID: */
PROVIDE(interrupt0 = DefaultHandler);
PROVIDE(__post_init = default_post_init);
/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
PROVIDE(_setup_interrupts = default_setup_interrupts);
/* # Multi-processing hook function
fn _mp_hook() -> bool;
This function is called from all the harts and must return true only for one hart,
which will perform memory initialization. For other harts it must return false
and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
*/
PROVIDE(_mp_hook = default_mp_hook);
/* # Start trap function override
By default uses the riscv crates default trap handler
but by providing the `_start_trap` symbol external crates can override.
*/
PROVIDE(_start_trap = default_start_trap);
SECTIONS
{
.text.dummy (NOLOAD) :
{
/* This section is intended to make _stext address work */
. = ABSOLUTE(_stext);
} > REGION_TEXT
.text _stext :
{
/* Put reset handler first in .text section so it ends up as the entry */
/* point of the program. */
KEEP(*(.init));
KEEP(*(.init.rust));
KEEP(*(.text.abort));
. = ALIGN(4);
*(.text .text.*);
_etext = .;
} > REGION_TEXT
_text_size = _etext - _stext + 8;
.rodata ORIGIN(ROM) + _text_size : AT(_text_size)
{
_srodata = .;
*(.srodata .srodata.*);
*(.rodata .rodata.*);
/* 4-byte align the end (VMA) of this section.
This is required by LLD to ensure the LMA of the following .data
section will have the correct alignment. */
. = ALIGN(4);
_erodata = .;
} > REGION_RODATA
_rodata_size = _erodata - _srodata + 8;
.data ORIGIN(RAM) : AT(_text_size + _rodata_size)
{
_data_start = .;
/* Must be called __global_pointer$ for linker relaxations to work. */
PROVIDE(__global_pointer$ = . + 0x800);
*(.sdata .sdata.* .sdata2 .sdata2.*);
*(.data .data.*);
. = ALIGN(4);
_data_end = .;
} > REGION_DATA
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;
.rtc_fast.text : AT(_text_size + _rodata_size + _data_size + _rwtext_size) {
_srtc_fast_text = .;
*(.rtc_fast.literal .rtc_fast.text .rtc_fast.literal.* .rtc_fast.text.*)
. = ALIGN(4);
_ertc_fast_text = .;
} > REGION_RTC_FAST
_fast_text_size = _ertc_fast_text - _srtc_fast_text + 8;
.rtc_fast.data : AT(_text_size + _rodata_size + _data_size + _rwtext_size + _fast_text_size)
{
_rtc_fast_data_start = ABSOLUTE(.);
*(.rtc_fast.data .rtc_fast.data.*)
. = ALIGN(4);
_rtc_fast_data_end = ABSOLUTE(.);
} > REGION_RTC_FAST
_rtc_fast_data_size = _rtc_fast_data_end - _rtc_fast_data_start + 8;
.rtc_fast.bss (NOLOAD) : ALIGN(4)
{
_rtc_fast_bss_start = ABSOLUTE(.);
*(.rtc_fast.bss .rtc_fast.bss.*)
. = ALIGN(4);
_rtc_fast_bss_end = ABSOLUTE(.);
} > REGION_RTC_FAST
.rtc_fast.noinit (NOLOAD) : ALIGN(4)
{
*(.rtc_fast.noinit .rtc_fast.noinit.*)
} > REGION_RTC_FAST
.bss (NOLOAD) :
{
_bss_start = .;
*(.sbss .sbss.* .bss .bss.*);
. = ALIGN(4);
_bss_end = .;
} > REGION_BSS
/* ### .uninit */
.uninit (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
__suninit = .;
*(.uninit .uninit.*);
. = ALIGN(4);
__euninit = .;
} > REGION_BSS
/* fictitious region that represents the memory available for the stack */
.stack (NOLOAD) :
{
_estack = .;
. = ABSOLUTE(_stack_start);
_sstack = .;
} > REGION_STACK
/* fake output .got section */
/* Dynamic relocations are unsupported. This section is only used to detect
relocatable code in the input files and raise an error if relocatable code
is found */
.got (INFO) :
{
KEEP(*(.got .got.*));
}
.eh_frame (INFO) : { KEEP(*(.eh_frame)) }
.eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
}
PROVIDE(_sidata = _erodata + 8);
PROVIDE(_irwtext = ORIGIN(ROM) + _text_size + _rodata_size + _data_size);
PROVIDE(_irtc_fast_text = ORIGIN(ROM) + _text_size + _rodata_size + _data_size + _rwtext_size);
PROVIDE(_irtc_fast_data = ORIGIN(ROM) + _text_size + _rodata_size + _data_size + _rwtext_size + _fast_text_size);
/* Do not exceed this mark in the error messages above | */
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
ASSERT(_stext % 4 == 0, "
ERROR(riscv-rt): `_stext` must be 4-byte aligned");
ASSERT(_data_start % 4 == 0 && _data_end % 4 == 0, "
BUG(riscv-rt): .data is not 4-byte aligned");
ASSERT(_sidata % 4 == 0, "
BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
ASSERT(_bss_start % 4 == 0 && _bss_end % 4 == 0, "
BUG(riscv-rt): .bss is not 4-byte aligned");
ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
ASSERT(SIZEOF(.got) == 0, "
.got section detected in the input files. Dynamic relocations are not
supported. If you are linking to C code compiled using the `gcc` crate
then modify your build script to compile the C code _without_ the
-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
details.");
/* Do not exceed this mark in the error messages above | */

11
esp32c6-hal/src/lib.rs
View File

@ -11,7 +11,6 @@
//! provided by [embedded-hal-async] and [embedded-io-async]
//! - `debug` - Enable debug features in the HAL (used for development)
//! - `defmt` - Enable [`defmt::Format`] on certain types
//! - `direct-boot` - Use the direct boot image format
//! - `direct-vectoring` - Enable direct vector table hooking support
//! - `eh1` - Implement the traits defined in the `1.0.0-xxx` pre-releases of
//! [embedded-hal], [embedded-hal-nb], and [embedded-io]
@ -58,16 +57,6 @@
//!
//! [ESP-IDF]: https://github.com/espressif/esp-idf
//! [App Image Format]: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/app_image_format.html
//!
//! #### Direct Boot
//!
//! This device additionally supports direct-boot, which allows an application
//! to be executed directly from flash, without using the second-stage
//! bootloader. For more information please see the
//! [esp32c3-direct-boot-example] in the Espressif organization on GitHub.
//!
//! [esp32c3-direct-boot-example]: https://github.com/espressif/esp32c3-direct-boot-example
#![no_std]
#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]

1
esp32h2-hal/Cargo.toml
View File

@ -60,7 +60,6 @@ default = ["rt", "vectored", "esp-hal-common/rv-zero-rtc-bss"]
async = ["esp-hal-common/async"]
debug = ["esp-hal-common/debug"]
defmt = ["esp-hal-common/defmt", "esp-println/defmt"]
direct-boot = ["esp-hal-common/rv-init-data", "esp-hal-common/rv-init-rtc-data"]
direct-vectoring = ["esp-hal-common/direct-vectoring"]
eh1 = ["esp-hal-common/eh1"]
interrupt-preemption = ["esp-hal-common/interrupt-preemption"]

24
esp32h2-hal/build.rs
View File

@ -1,6 +1,5 @@
use std::{env, error::Error, fs, path::PathBuf};
#[cfg(not(feature = "direct-boot"))]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
@ -21,26 +20,3 @@ fn main() -> Result<(), Box<dyn Error>> {
Ok(())
}
#[cfg(feature = "direct-boot")]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out.display());
fs::copy("ld/db-esp32h2-memory.x", out.join("memory.x"))?;
fs::copy("ld/db-esp32h2-link.x", out.join("esp32h2-link.x"))?;
fs::copy("ld/db-riscv-link.x", out.join("riscv-link.x"))?;
fs::copy("ld/db-linkall.x", out.join("linkall.x"))?;
fs::copy("ld/rom-functions.x", out.join("rom-functions.x"))?;
// Only re-run the build script when memory.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=ld/memory.x");
#[cfg(feature = "defmt")]
println!("cargo:rustc-link-arg=-Tdefmt.x");
Ok(())
}

14
esp32h2-hal/ld/db-esp32h2-link.x
View File

@ -1,14 +0,0 @@
INCLUDE memory.x
SECTIONS
{
.header : AT(0)
{
LONG(0xaedb041d)
LONG(0xaedb041d)
} > ROM
}
_stext = ORIGIN(ROM) + 8;
INCLUDE riscv-link.x

38
esp32h2-hal/ld/db-esp32h2-memory.x
View File

@ -1,38 +0,0 @@
MEMORY
{
/* MEMORY_MAP = [
[0x00000000, 0x00010000, "PADDING"],
[0x42800000, 0x43000000, "DROM"],
[0x40800000, 0x40850000, "DRAM"],
[0x40800000, 0x40850000, "BYTE_ACCESSIBLE"],
[0x4001С400, 0x40020000, "DROM_MASK"],
[0x40000000, 0x4001С400, "IROM_MASK"],
[0x42000000, 0x42800000, "IROM"],
[0x40800000, 0x40850000, "IRAM"],
[0x50000000, 0x50001000, "RTC_IRAM"],
[0x50000000, 0x50001000, "RTC_DRAM"],
[0x600FE000, 0x60100000, "MEM_INTERNAL2"],
] */
/* 320K of on soc RAM, 16K reserved for cache */
ICACHE : ORIGIN = 0x40800000, LENGTH = 16K
RAM : ORIGIN = 0x40800000 + 16K, LENGTH = 320K - 16K
/* External flash */
ROM : ORIGIN = 0x42000000, LENGTH = 0x400000
/* RTC fast memory (executable). Persists over deep sleep. */
RTC_FAST : ORIGIN = 0x50000000, LENGTH = 16K /*- ESP_BOOTLOADER_RESERVE_RTC*/
}
REGION_ALIAS("REGION_TEXT", ROM);
REGION_ALIAS("REGION_RODATA", ROM);
REGION_ALIAS("REGION_DATA", RAM);
REGION_ALIAS("REGION_BSS", RAM);
REGION_ALIAS("REGION_STACK", RAM);
REGION_ALIAS("REGION_RWTEXT", RAM);
REGION_ALIAS("REGION_RTC_FAST", RTC_FAST);

3
esp32h2-hal/ld/db-linkall.x
View File

@ -1,3 +0,0 @@
INCLUDE "esp32h2-link.x"
INCLUDE "hal-defaults.x"
INCLUDE "rom-functions.x"

216
esp32h2-hal/ld/db-riscv-link.x
View File

@ -1,216 +0,0 @@
ENTRY(_start)
PROVIDE(_stext = ORIGIN(REGION_TEXT));
PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
PROVIDE(_max_hart_id = 0);
PROVIDE(UserSoft = DefaultHandler);
PROVIDE(SupervisorSoft = DefaultHandler);
PROVIDE(MachineSoft = DefaultHandler);
PROVIDE(UserTimer = DefaultHandler);
PROVIDE(SupervisorTimer = DefaultHandler);
PROVIDE(MachineTimer = DefaultHandler);
PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler);
/* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6 and ESP32-H2 have
IDs 0-31, so we much define the handler for the one additional interrupt
ID: */
PROVIDE(interrupt0 = DefaultHandler);
PROVIDE(__post_init = default_post_init);
/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
PROVIDE(_setup_interrupts = default_setup_interrupts);
/* # Multi-processing hook function
fn _mp_hook() -> bool;
This function is called from all the harts and must return true only for one hart,
which will perform memory initialization. For other harts it must return false
and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
*/
PROVIDE(_mp_hook = default_mp_hook);
/* # Start trap function override
By default uses the riscv crates default trap handler
but by providing the `_start_trap` symbol external crates can override.
*/
PROVIDE(_start_trap = default_start_trap);
SECTIONS
{
.text.dummy (NOLOAD) :
{
/* This section is intended to make _stext address work */
. = ABSOLUTE(_stext);
} > REGION_TEXT
.text _stext :
{
/* Put reset handler first in .text section so it ends up as the entry */
/* point of the program. */
KEEP(*(.init));
KEEP(*(.init.rust));
KEEP(*(.text.abort));
. = ALIGN(4);
*(.text .text.*);
_etext = .;
} > REGION_TEXT
_text_size = _etext - _stext + 8;
.rodata ORIGIN(ROM) + _text_size : AT(_text_size)
{
_srodata = .;
*(.srodata .srodata.*);
*(.rodata .rodata.*);
/* 4-byte align the end (VMA) of this section.
This is required by LLD to ensure the LMA of the following .data
section will have the correct alignment. */
. = ALIGN(4);
_erodata = .;
} > REGION_RODATA
_rodata_size = _erodata - _srodata + 8;
.data ORIGIN(RAM) : AT(_text_size + _rodata_size)
{
_data_start = .;
/* Must be called __global_pointer$ for linker relaxations to work. */
PROVIDE(__global_pointer$ = . + 0x800);
*(.sdata .sdata.* .sdata2 .sdata2.*);
*(.data .data.*);
. = ALIGN(4);
_data_end = .;
} > REGION_DATA
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;
.rtc_fast.text : AT(_text_size + _rodata_size + _data_size + _rwtext_size) {
_srtc_fast_text = .;
*(.rtc_fast.literal .rtc_fast.text .rtc_fast.literal.* .rtc_fast.text.*)
. = ALIGN(4);
_ertc_fast_text = .;
} > REGION_RTC_FAST
_fast_text_size = _ertc_fast_text - _srtc_fast_text + 8;
.rtc_fast.data : AT(_text_size + _rodata_size + _data_size + _rwtext_size + _fast_text_size)
{
_rtc_fast_data_start = ABSOLUTE(.);
*(.rtc_fast.data .rtc_fast.data.*)
. = ALIGN(4);
_rtc_fast_data_end = ABSOLUTE(.);
} > REGION_RTC_FAST
_rtc_fast_data_size = _rtc_fast_data_end - _rtc_fast_data_start + 8;
.rtc_fast.bss (NOLOAD) : ALIGN(4)
{
_rtc_fast_bss_start = ABSOLUTE(.);
*(.rtc_fast.bss .rtc_fast.bss.*)
. = ALIGN(4);
_rtc_fast_bss_end = ABSOLUTE(.);
} > REGION_RTC_FAST
.rtc_fast.noinit (NOLOAD) : ALIGN(4)
{
*(.rtc_fast.noinit .rtc_fast.noinit.*)
} > REGION_RTC_FAST
.bss (NOLOAD) :
{
_bss_start = .;
*(.sbss .sbss.* .bss .bss.*);
. = ALIGN(4);
_bss_end = .;
} > REGION_BSS
/* ### .uninit */
.uninit (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
__suninit = .;
*(.uninit .uninit.*);
. = ALIGN(4);
__euninit = .;
} > REGION_BSS
/* fictitious region that represents the memory available for the stack */
.stack (NOLOAD) :
{
_estack = .;
. = ABSOLUTE(_stack_start);
_sstack = .;
} > REGION_STACK
/* fake output .got section */
/* Dynamic relocations are unsupported. This section is only used to detect
relocatable code in the input files and raise an error if relocatable code
is found */
.got (INFO) :
{
KEEP(*(.got .got.*));
}
.eh_frame (INFO) : { KEEP(*(.eh_frame)) }
.eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
}
PROVIDE(_sidata = _erodata + 8);
PROVIDE(_irwtext = ORIGIN(ROM) + _text_size + _rodata_size + _data_size);
PROVIDE(_irtc_fast_text = ORIGIN(ROM) + _text_size + _rodata_size + _data_size + _rwtext_size);
PROVIDE(_irtc_fast_data = ORIGIN(ROM) + _text_size + _rodata_size + _data_size + _rwtext_size + _fast_text_size);
/* Do not exceed this mark in the error messages above | */
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
ASSERT(_stext % 4 == 0, "
ERROR(riscv-rt): `_stext` must be 4-byte aligned");
ASSERT(_data_start % 4 == 0 && _data_end % 4 == 0, "
BUG(riscv-rt): .data is not 4-byte aligned");
ASSERT(_sidata % 4 == 0, "
BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
ASSERT(_bss_start % 4 == 0 && _bss_end % 4 == 0, "
BUG(riscv-rt): .bss is not 4-byte aligned");
ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
ASSERT(SIZEOF(.got) == 0, "
.got section detected in the input files. Dynamic relocations are not
supported. If you are linking to C code compiled using the `gcc` crate
then modify your build script to compile the C code _without_ the
-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
details.");
/* Do not exceed this mark in the error messages above | */

11
esp32h2-hal/src/lib.rs
View File

@ -11,7 +11,6 @@
//! provided by [embedded-hal-async] and [embedded-io-async]
//! - `debug` - Enable debug features in the HAL (used for development)
//! - `defmt` - Enable [`defmt::Format`] on certain types
//! - `direct-boot` - Use the direct boot image format
//! - `direct-vectoring` - Enable direct vector table hooking support
//! - `eh1` - Implement the traits defined in the `1.0.0-xxx` pre-releases of
//! [embedded-hal], [embedded-hal-nb], and [embedded-io]
@ -58,16 +57,6 @@
//!
//! [ESP-IDF]: https://github.com/espressif/esp-idf
//! [App Image Format]: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/app_image_format.html
//!
//! #### Direct Boot
//!
//! This device additionally supports direct-boot, which allows an application
//! to be executed directly from flash, without using the second-stage
//! bootloader. For more information please see the
//! [esp32c3-direct-boot-example] in the Espressif organization on GitHub.
//!
//! [esp32c3-direct-boot-example]: https://github.com/espressif/esp32c3-direct-boot-example
#![no_std]
#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]

1
esp32s3-hal/Cargo.toml
View File

@ -60,7 +60,6 @@ default = ["rt", "vectored"]
async = ["esp-hal-common/async"]
debug = ["esp-hal-common/debug"]
defmt = ["esp-hal-common/defmt", "esp-println/defmt"]
direct-boot = ["r0"]
eh1 = ["esp-hal-common/eh1"]
log = ["esp-hal-common/log", "esp-println/log"]
rt = []

23
esp32s3-hal/build.rs
View File

@ -1,6 +1,5 @@
use std::{env, error::Error, fs, path::PathBuf};
#[cfg(not(feature = "direct-boot"))]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
@ -21,25 +20,3 @@ fn main() -> Result<(), Box<dyn Error>> {
Ok(())
}
#[cfg(feature = "direct-boot")]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out.display());
fs::copy("ld/db-memory.x", out.join("memory.x"))?;
fs::copy("ld/db-esp32s3.x", out.join("link-esp32s3.x"))?;
fs::copy("ld/linkall.x", out.join("linkall.x"))?;
fs::copy("ld/rom-functions.x", out.join("rom-functions.x"))?;
// Only re-run the build script when memory.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=ld/memory.x");
#[cfg(feature = "defmt")]
println!("cargo:rustc-link-arg=-Tdefmt.x");
Ok(())
}

277
esp32s3-hal/ld/db-esp32s3.x
View File

@ -1,277 +0,0 @@
/* before memory.x to allow override */
ENTRY(ESP32Reset)
_stack_region_top = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg);
_stack_region_bottom = _stack_end;
/*
use the whole remaining memory as core-0's stack
*/
_stack_end_cpu0 = _stack_region_top;
_stack_start_cpu0 = _stack_region_bottom;
EXTERN(DefaultHandler);
INCLUDE "device.x"
/* after memory.x to allow override */
PROVIDE(__pre_init = DefaultPreInit);
PROVIDE(__zero_bss = default_mem_hook);
PROVIDE(__init_data = default_mem_hook);
PROVIDE(__post_init = default_post_init);
/*INCLUDE exception.x*/
/* exception vector for the ESP32, requiring high priority interrupts and register window support */
/* high level exception/interrupt routines, which can be override with Rust functions */
PROVIDE(__exception = __default_exception);
PROVIDE(__user_exception = __default_user_exception);
PROVIDE(__double_exception = __default_double_exception);
PROVIDE(__level_1_interrupt = __default_interrupt);
PROVIDE(__level_2_interrupt = __default_interrupt);
PROVIDE(__level_3_interrupt = __default_interrupt);
PROVIDE(__level_4_interrupt = __default_interrupt);
PROVIDE(__level_5_interrupt = __default_interrupt);
PROVIDE(__level_6_interrupt = __default_interrupt);
PROVIDE(__level_7_interrupt = __default_interrupt);
/* low level exception/interrupt, which must be overridden using naked functions */
PROVIDE(__naked_user_exception = __default_naked_exception);
PROVIDE(__naked_kernel_exception = __default_naked_exception);
PROVIDE(__naked_double_exception = __default_naked_double_exception);
PROVIDE(__naked_level_2_interrupt = __default_naked_level_2_interrupt);
PROVIDE(__naked_level_3_interrupt = __default_naked_level_3_interrupt);
PROVIDE(__naked_level_4_interrupt = __default_naked_level_4_interrupt);
PROVIDE(__naked_level_5_interrupt = __default_naked_level_5_interrupt);
PROVIDE(__naked_level_6_interrupt = __default_naked_level_6_interrupt);
PROVIDE(__naked_level_7_interrupt = __default_naked_level_7_interrupt);
/* needed to force inclusion of the vectors */
EXTERN(__default_exception);
EXTERN(__default_double_exception);
EXTERN(__default_interrupt);
/* high level CPU interrupts */
PROVIDE(Timer0 = __default_user_exception);
PROVIDE(Timer1 = __default_user_exception);
PROVIDE(Timer2 = __default_user_exception);
PROVIDE(Timer3 = __default_user_exception);
PROVIDE(Profiling = __default_user_exception);
PROVIDE(NMI = __default_user_exception);
PROVIDE(Software0 = __default_user_exception);
PROVIDE(Software1 = __default_user_exception);
/* low level exception/interrupt, which must be overridden using naked functions */
EXTERN(__default_naked_exception);
EXTERN(__default_naked_double_exception);
EXTERN(__default_naked_level_2_interrupt);
EXTERN(__default_naked_level_3_interrupt);
EXTERN(__default_naked_level_4_interrupt);
EXTERN(__default_naked_level_5_interrupt);
EXTERN(__default_naked_level_6_interrupt);
EXTERN(__default_naked_level_7_interrupt);
SECTIONS {
.pre_header (NOLOAD) : AT(0)
{
. = . + 0x400;
} > irom_seg
.header ORIGIN(ROTEXT) + 0x400 : AT(0x400)
{
LONG(0xaedb041d)
LONG(0xaedb041d)
} > irom_seg
.text ORIGIN(ROTEXT) + 0x408 : AT(0x408)
{
_stext = .;
. = ALIGN (4);
_text_start = ABSOLUTE(.);
. = ALIGN (4);
KEEP(*(.init));
*(.literal .text .literal.* .text.*)
. = ALIGN (4);
_text_end = ABSOLUTE(.);
_etext = .;
} > REGION_TEXT
_text_size = _etext - _stext;
.rodata ORIGIN(RODATA) + 0x408 + _text_size : AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header))
{
. = ALIGN (4);
_rodata_start = ABSOLUTE(.);
*(.rodata .rodata.*)
. = ALIGN (4);
_rodata_end = ABSOLUTE(.);
} > REGION_RODATA
.rwtext ORIGIN(RWTEXT) + 0x408 + _text_size + SIZEOF(.rodata) :
AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata))
{
_irwtext = ORIGIN(RODATA) + 0x408 + _text_size + SIZEOF(.rodata);
_srwtext = .;
. = ALIGN (4);
. = ALIGN(0x1000);
_init_start = ABSOLUTE(.);
KEEP(*(.WindowOverflow4.text));
. = ALIGN(64);
KEEP(*(.WindowUnderflow4.text));
. = ALIGN(64);
KEEP(*(.WindowOverflow8.text));
. = ALIGN(64);
KEEP(*(.WindowUnderflow8.text));
. = ALIGN(64);
KEEP(*(.WindowOverflow12.text));
. = ALIGN(64);
KEEP(*(.WindowUnderflow12.text));
. = ALIGN(64);
KEEP(*(.Level2InterruptVector.text));
. = ALIGN(64);
KEEP(*(.Level3InterruptVector.text));
. = ALIGN(64);
KEEP(*(.Level4InterruptVector.text));
. = ALIGN(64);
KEEP(*(.Level5InterruptVector.text));
. = ALIGN(64);
KEEP(*(.DebugExceptionVector.text));
. = ALIGN(64);
KEEP(*(.NMIExceptionVector.text));
. = ALIGN(64);
KEEP(*(.KernelExceptionVector.text));
. = ALIGN(64);
KEEP(*(.UserExceptionVector.text));
. = ALIGN(128);
KEEP(*(.DoubleExceptionVector.text));
. = ALIGN(0x400);
_init_end = ABSOLUTE(.);
*(.rwtext.literal .rwtext .rwtext.literal.* .rwtext.*)
. = ALIGN (4);
_erwtext = .;
} > REGION_RWTEXT
.data ORIGIN(RWDATA) :
AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext))
{
_data_start = ABSOLUTE(.);
. = ALIGN (4);
*(.data .data.*)
. = ALIGN (4);
_data_end = ABSOLUTE(.);
} > REGION_DATA
/* LMA of .data */
_sidata = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext);
.bss (NOLOAD) : ALIGN(4)
{
_bss_start = ABSOLUTE(.);
. = ALIGN (4);
*(.bss .bss.* COMMON)
. = ALIGN (4);
_bss_end = ABSOLUTE(.);
} > REGION_BSS
.noinit (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
*(.noinit .noinit.*)
. = ALIGN (4);
} > REGION_BSS
/* must be last segment using RWDATA */
.stack_end (NOLOAD) : ALIGN(4)
{
. = ALIGN (4);
_stack_end = ABSOLUTE(.);
} > REGION_STACK
.rtc_fast.text ORIGIN(rtc_fast_seg) :
AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) + SIZEOF(.data) + SIZEOF(.bss) + SIZEOF(.noinit))
{
. = ALIGN(4);
_rtc_fast_text_start = ABSOLUTE(.);
*(.rtc_fast.literal .rtc_fast.text .rtc_fast.literal.* .rtc_fast.text.*)
. = ALIGN(4);
_rtc_fast_text_end = ABSOLUTE(.);
} > REGION_RTC_FAST
_irtc_fast_text = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) + SIZEOF(.data) + SIZEOF(.bss) + SIZEOF(.noinit);
.rtc_fast.data ORIGIN(rtc_fast_seg) + SIZEOF(.rtc_fast.text) :
AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) + SIZEOF(.data) + SIZEOF(.bss) + SIZEOF(.noinit) + SIZEOF(.rtc_fast.text) )
{
. = ALIGN(4);
_rtc_fast_data_start = ABSOLUTE(.);
*(.rtc_fast.data .rtc_fast.data.*)
. = ALIGN(4);
_rtc_fast_data_end = ABSOLUTE(.);
} > REGION_RTC_FAST
_irtc_fast_data = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) + SIZEOF(.data) + SIZEOF(.bss) + SIZEOF(.noinit) + SIZEOF(.rtc_fast.text);
.rtc_fast.bss ORIGIN(rtc_fast_seg) + SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) (NOLOAD) :
AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) + SIZEOF(.data) + SIZEOF(.bss) + SIZEOF(.noinit) + SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data))
{
. = ALIGN(4);
_rtc_fast_bss_start = ABSOLUTE(.);
*(.rtc_fast.bss .rtc_fast.bss.*)
. = ALIGN (4);
_rtc_fast_bss_end = ABSOLUTE(.);
} > REGION_RTC_FAST
.rtc_fast.noinit ORIGIN(rtc_fast_seg) + SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss) (NOLOAD) :
{
. = ALIGN(4);
*(.rtc_fast.noinit .rtc_fast.noinit.*)
. = ALIGN (4);
} > REGION_RTC_FAST
.rtc_slow.text ORIGIN(rtc_slow_seg) :
AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss))
{
. = ALIGN(4);
_rtc_slow_text_start = ABSOLUTE(.);
*(.rtc_slow.literal .rtc_slow.text .rtc_slow.literal.* .rtc_slow.text.*)
. = ALIGN(4);
_rtc_slow_text_end = ABSOLUTE(.);
} > REGION_RTC_SLOW
_irtc_slow_text = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss);
.rtc_slow.data ORIGIN(rtc_slow_seg) + SIZEOF(.rtc_slow.text) :
AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss) + SIZEOF(.rtc_slow.text))
{
. = ALIGN(4);
_rtc_slow_data_start = ABSOLUTE(.);
*(.rtc_slow.data .rtc_slow.data.*)
. = ALIGN(4);
_rtc_slow_data_end = ABSOLUTE(.);
} > REGION_RTC_SLOW
_irtc_slow_data = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss) + SIZEOF(.rtc_slow.text);
.rtc_slow.bss ORIGIN(rtc_slow_seg) + SIZEOF(.rtc_slow.text) + SIZEOF(.rtc_slow.data) (NOLOAD) :
AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss) + SIZEOF(.rtc_slow.text) + SIZEOF(.rtc_slow.data))
{
. = ALIGN(4);
_rtc_slow_bss_start = ABSOLUTE(.);
*(.rtc_slow.bss .rtc_slow.bss.*)
. = ALIGN (4);
_rtc_slow_bss_end = ABSOLUTE(.);
} > REGION_RTC_SLOW
.rtc_slow.noinit ORIGIN(rtc_slow_seg) + SIZEOF(.rtc_slow.text) + SIZEOF(.rtc_slow.data) + SIZEOF(.rtc_slow.bss) (NOLOAD) :
{
. = ALIGN(4);
*(.rtc_slow.noinit .rtc_slow.noinit.*)
. = ALIGN (4);
} > REGION_RTC_SLOW
}

42
esp32s3-hal/ld/db-memory.x
View File

@ -1,42 +0,0 @@
/* override entry point */
ENTRY(ESP32Reset)
/* reserved at the start of DRAM */
RESERVE_DRAM = 0x8000;
/* Specify main memory areas */
MEMORY
{
iram_seg ( RX ) : ORIGIN = 0x40370400 + RESERVE_DRAM, len = 328k - 0x400
dram_seg ( RW ) : ORIGIN = 0x3FC80000 + RESERVE_DRAM, len = 328k - RESERVE_DRAM
reserved_for_boot_seg : ORIGIN = 0x3FFDC200, len = 144k /* ???? SRAM1; reserved for static ROM usage; can be used for heap */
/* external flash
The 0x20 offset is a convenience for the app binary image generation.
Flash cache has 64KB pages. The .bin file which is flashed to the chip
has a 0x18 byte file header, and each segment has a 0x08 byte segment
header. Setting this offset makes it simple to meet the flash cache MMU's
constraint that (paddr % 64KB == vaddr % 64KB).)
*/
irom_seg ( RX ) : ORIGIN = 0x42000000, len = 4M
drom_seg ( R ) : ORIGIN = 0x3C000000, len = 4M
/* RTC fast memory (executable). Persists over deep sleep. Only for core 0 (PRO_CPU) */
rtc_fast_seg(RWX) : ORIGIN = 0x600fe000, len = 8k
/* RTC slow memory (data accessible). Persists over deep sleep. */
rtc_slow_seg(RW) : ORIGIN = 0x50000000, len = 8k
}
REGION_ALIAS("REGION_TEXT", irom_seg);
REGION_ALIAS("REGION_RODATA", drom_seg);
REGION_ALIAS("REGION_DATA", dram_seg);
REGION_ALIAS("REGION_BSS", dram_seg);
REGION_ALIAS("REGION_STACK", dram_seg);
REGION_ALIAS("REGION_RWTEXT", iram_seg);
REGION_ALIAS("REGION_RTC_FAST", rtc_fast_seg);
REGION_ALIAS("REGION_RTC_SLOW", rtc_slow_seg);

136
esp32s3-hal/src/lib.rs
View File

@ -11,7 +11,6 @@
//! provided by [embedded-hal-async] and [embedded-io-async]
//! - `debug` - Enable debug features in the HAL (used for development)
//! - `defmt` - Enable [`defmt::Format`] on certain types
//! - `direct-boot` - Use the direct boot image format
//! - `eh1` - Implement the traits defined in the `1.0.0-xxx` pre-releases of
//! [embedded-hal], [embedded-hal-nb], and [embedded-io]
//! - `embassy` - Enable support for [embassy], a modern asynchronous embedded
@ -66,138 +65,11 @@
//!
//! [ESP-IDF]: https://github.com/espressif/esp-idf
//! [App Image Format]: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/app_image_format.html
//!
//! #### Direct Boot
//!
//! This device additionally supports direct-boot, which allows an application
//! to be executed directly from flash, without using the second-stage
//! bootloader. For more information please see the
//! [esp32c3-direct-boot-example] in the Espressif organization on GitHub.
//!
//! [esp32c3-direct-boot-example]: https://github.com/espressif/esp32c3-direct-boot-example
#![no_std]
#![cfg_attr(
feature = "direct-boot",
feature(asm_experimental_arch),
feature(naked_functions)
)]
#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
pub use esp_hal_common::*;
#[cfg(all(feature = "rt", feature = "direct-boot"))]
#[doc(hidden)]
#[no_mangle]
#[link_section = ".init"]
#[naked]
unsafe extern "C" fn init() {
core::arch::asm!("call0 startup_direct_boot", options(noreturn));
}
#[cfg(all(feature = "rt", feature = "direct-boot"))]
#[doc(hidden)]
#[no_mangle]
pub unsafe fn startup_direct_boot() -> ! {
// These symbols are from `memory.x`
extern "C" {
static mut _rtc_fast_bss_start: u32;
static mut _rtc_fast_bss_end: u32;
static mut _rtc_slow_bss_start: u32;
static mut _rtc_slow_bss_end: u32;
// Boundaries of the .rtc_fast.text section
static mut _rtc_fast_text_start: u32;
static mut _rtc_fast_text_end: u32;
static mut _irtc_fast_text: u32;
// Boundaries of the .rtc_fast.data section
static mut _rtc_fast_data_start: u32;
static mut _rtc_fast_data_end: u32;
static mut _irtc_fast_data: u32;
// Boundaries of the .rtc_slow.text section
static mut _rtc_slow_text_start: u32;
static mut _rtc_slow_text_end: u32;
static mut _irtc_slow_text: u32;
// Boundaries of the .rtc_slow.data section
static mut _rtc_slow_data_start: u32;
static mut _rtc_slow_data_end: u32;
static mut _irtc_slow_data: u32;
static mut _stack_end_cpu0: u32;
}
// set stack pointer to end of memory: no need to retain stack up to this point
xtensa_lx::set_stack_pointer(&mut _stack_end_cpu0);
// copy rtc data from flash to destinations
r0::init_data(
&mut _rtc_fast_data_start,
&mut _rtc_fast_data_end,
&_irtc_fast_data,
);
r0::init_data(
&mut _rtc_fast_text_start,
&mut _rtc_fast_text_end,
&_irtc_fast_text,
);
r0::init_data(
&mut _rtc_slow_data_start,
&mut _rtc_slow_data_end,
&_irtc_slow_data,
);
r0::init_data(
&mut _rtc_slow_text_start,
&mut _rtc_slow_text_end,
&_irtc_slow_text,
);
// Initialize RTC RAM
esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end);
// first of all copy rwtext
extern "C" {
// Boundaries of the .iram section
static mut _srwtext: u32;
static mut _erwtext: u32;
static mut _irwtext: u32;
}
r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext);
// do some configurations for compatability with the 2nd stage bootloader
// this is a workaround and ideally we should deal with these settings in other
// places
(&*crate::peripherals::TIMG0::PTR)
.int_ena_timers
.modify(|_, w| w.t0_int_ena().set_bit().t1_int_ena().set_bit());
(&*crate::peripherals::TIMG1::PTR)
.int_ena_timers
.modify(|_, w| w.t0_int_ena().set_bit().t1_int_ena().set_bit());
(&*crate::peripherals::RTC_CNTL::PTR)
.swd_wprotect
.write(|w| w.bits(0x8f1d312a));
(&*crate::peripherals::RTC_CNTL::PTR)
.swd_conf
.modify(|_, w| w.swd_disable().set_bit());
(&*crate::peripherals::RTC_CNTL::PTR)
.swd_wprotect
.write(|w| w.bits(0));
(&*crate::peripherals::SYSTEM::PTR)
.sysclk_conf
.modify(|_, w| w.soc_clk_sel().bits(1));
esp_hal_common::xtensa_lx_rt::Reset();
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".rwtext"]
@ -271,13 +143,7 @@ pub unsafe extern "C" fn ESP32Reset() -> ! {
#[no_mangle]
#[rustfmt::skip]
pub extern "Rust" fn __init_data() -> bool {
#[cfg(feature = "direct-boot")]
let res = true;
#[cfg(not(feature = "direct-boot"))]
let res = false;
res
false
}
#[export_name = "__post_init"]