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https://github.com/esp-rs/esp-hal.git
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TIMG: Fix interrupt handler setup (#1715)
Co-authored-by: Dominic Fischer <git@dominicfischer.me>
This commit is contained in:
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@ -19,6 +19,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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### Fixed
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### Fixed
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- TIMG: Fix interrupt handler setup (#1714)
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### Changed
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### Changed
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- Refactor `Dac1`/`Dac2` drivers into a single `Dac` driver (#1661)
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- Refactor `Dac1`/`Dac2` drivers into a single `Dac` driver (#1661)
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@ -32,7 +32,7 @@
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//! peripherals.TIMG0,
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//! peripherals.TIMG0,
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//! &clocks,
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//! &clocks,
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//! Some(TimerInterrupts {
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//! Some(TimerInterrupts {
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//! timer0_t0: Some(tg0_t0_level),
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//! timer0: Some(tg0_t0_level),
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//! ..Default::default()
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//! ..Default::default()
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//! }),
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//! }),
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//! );
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//! );
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@ -85,21 +85,13 @@ use crate::{
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/// Interrupts which can be registered in [Blocking] mode
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/// Interrupts which can be registered in [Blocking] mode
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#[derive(Debug, Default)]
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#[derive(Debug, Default)]
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pub struct TimerInterrupts {
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pub struct TimerInterrupts {
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/// T0 Interrupt for [`Timer0`]
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/// Interrupt for [`Timer0`]
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pub timer0_t0: Option<InterruptHandler>,
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pub timer0: Option<InterruptHandler>,
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/// T1 Interrupt for [`Timer0`]
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pub timer0_t1: Option<InterruptHandler>,
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/// WDT Interrupt for [`Timer0`]
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pub timer0_wdt: Option<InterruptHandler>,
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/// T0 Interrupt for [`Timer1`]
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#[cfg(timg_timer1)]
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#[cfg(timg_timer1)]
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pub timer1_t0: Option<InterruptHandler>,
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/// Interrupt for [`Timer1`]
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/// T1 Interrupt for [`Timer1`]
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pub timer1: Option<InterruptHandler>,
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#[cfg(timg_timer1)]
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/// WDT Interrupt
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pub timer1_t1: Option<InterruptHandler>,
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pub wdt: Option<InterruptHandler>,
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/// WDT Interrupt for [`Timer1`]
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#[cfg(timg_timer1)]
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pub timer1_wdt: Option<InterruptHandler>,
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}
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}
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/// A timer group consisting of up to 2 timers (chip dependent) and a watchdog
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/// A timer group consisting of up to 2 timers (chip dependent) and a watchdog
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@ -274,50 +266,43 @@ where
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);
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);
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if let Some(isr) = isr {
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if let Some(isr) = isr {
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if let Some(handler) = isr.timer0_t0 {
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if let Some(handler) = isr.timer0 {
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let interrupt = match T::id() {
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0 => Interrupt::TG0_T0_LEVEL,
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#[cfg(timg1)]
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1 => Interrupt::TG1_T0_LEVEL,
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_ => unreachable!(),
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};
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unsafe {
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unsafe {
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interrupt::bind_interrupt(Interrupt::TG0_T0_LEVEL, handler.handler());
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interrupt::bind_interrupt(interrupt, handler.handler());
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interrupt::enable(Interrupt::TG0_T0_LEVEL, handler.priority()).unwrap();
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interrupt::enable(interrupt, handler.priority()).unwrap();
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}
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}
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#[cfg(any(esp32, esp32s2, esp32s3))]
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if let Some(handler) = isr.timer0_t1 {
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unsafe {
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interrupt::bind_interrupt(Interrupt::TG0_T1_LEVEL, handler.handler());
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interrupt::enable(Interrupt::TG0_T1_LEVEL, handler.priority()).unwrap();
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}
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}
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if let Some(handler) = isr.timer0_wdt {
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unsafe {
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interrupt::bind_interrupt(Interrupt::TG0_WDT_LEVEL, handler.handler());
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interrupt::enable(Interrupt::TG0_WDT_LEVEL, handler.priority()).unwrap();
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}
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}
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}
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}
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#[cfg(timg_timer1)]
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#[cfg(timg_timer1)]
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{
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if let Some(handler) = isr.timer1 {
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if let Some(handler) = isr.timer1_t0 {
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let interrupt = match T::id() {
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0 => Interrupt::TG0_T1_LEVEL,
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#[cfg(timg1)]
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1 => Interrupt::TG1_T1_LEVEL,
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_ => unreachable!(),
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};
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unsafe {
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unsafe {
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interrupt::bind_interrupt(Interrupt::TG1_T0_LEVEL, handler.handler());
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interrupt::bind_interrupt(interrupt, handler.handler());
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interrupt::enable(Interrupt::TG1_T0_LEVEL, handler.priority()).unwrap();
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interrupt::enable(interrupt, handler.priority()).unwrap();
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}
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}
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}
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}
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#[cfg(any(esp32, esp32s2, esp32s3))]
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if let Some(handler) = isr.wdt {
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if let Some(handler) = isr.timer1_t1 {
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let interrupt = match T::id() {
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0 => Interrupt::TG0_WDT_LEVEL,
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#[cfg(timg1)]
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1 => Interrupt::TG1_WDT_LEVEL,
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_ => unreachable!(),
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};
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unsafe {
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unsafe {
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interrupt::bind_interrupt(Interrupt::TG1_T1_LEVEL, handler.handler());
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interrupt::bind_interrupt(interrupt, handler.handler());
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interrupt::enable(Interrupt::TG1_T1_LEVEL, handler.priority()).unwrap();
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interrupt::enable(interrupt, handler.priority()).unwrap();
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}
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}
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if let Some(handler) = isr.timer1_wdt {
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unsafe {
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interrupt::bind_interrupt(Interrupt::TG1_WDT_LEVEL, handler.handler());
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interrupt::enable(Interrupt::TG1_WDT_LEVEL, handler.priority()).unwrap();
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}
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}
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}
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}
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}
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}
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}
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@ -39,7 +39,7 @@ fn main() -> ! {
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peripherals.TIMG0,
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peripherals.TIMG0,
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&clocks,
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&clocks,
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Some(TimerInterrupts {
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Some(TimerInterrupts {
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timer0_t0: Some(tg0_t0_level),
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timer0: Some(tg0_t0_level),
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..Default::default()
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..Default::default()
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}),
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}),
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);
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);
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@ -33,7 +33,7 @@ fn main() -> ! {
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peripherals.TIMG0,
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peripherals.TIMG0,
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&clocks,
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&clocks,
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Some(TimerInterrupts {
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Some(TimerInterrupts {
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timer0_t0: Some(tg0_t0_level),
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timer0: Some(tg0_t0_level),
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..Default::default()
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..Default::default()
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}),
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}),
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);
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);
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