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Update to 1.85 toolchain (#3146)

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* test esp 1.85 toolchain

* clippy lints
This commit is contained in:
Scott Mabin 2025-02-20 12:13:02 +00:00 committed by GitHub
parent 53d57bd01a
commit b38d5cc8d5
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GPG Key ID: B5690EEEBB952194
18 changed files with 23 additions and 22 deletions
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2
.github/workflows/ci.yml vendored
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@ -72,7 +72,7 @@ jobs:
- uses: esp-rs/xtensa-toolchain@v1.5
with:
ldproxy: false
version: 1.84.0.0
version: 1.85.0.0
# Install the Rust stable toolchain for RISC-V devices:
- uses: dtolnay/rust-toolchain@v1
with:

2
.github/workflows/documentation.yml vendored
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@ -36,7 +36,7 @@ jobs:
with:
default: true
ldproxy: false
version: 1.84.0.0
version: 1.85.0.0
- name: Checkout repository
uses: actions/checkout@v4

2
.github/workflows/hil.yml vendored
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@ -115,7 +115,7 @@ jobs:
buildtargets: ${{ matrix.target.soc }}
default: true
ldproxy: false
version: 1.84.0.0
version: 1.85.0.0
- name: Build tests
run: cargo xtask build-tests ${{ matrix.target.soc }}

4
esp-hal/src/interrupt/xtensa.rs
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@ -157,7 +157,7 @@ pub fn enable_direct(interrupt: Interrupt, cpu_interrupt: CpuInterrupt) -> Resul
map(Cpu::current(), interrupt, cpu_interrupt);
xtensa_lx::interrupt::enable_mask(
xtensa_lx::interrupt::get_mask() | 1 << cpu_interrupt as u32,
xtensa_lx::interrupt::get_mask() | (1 << cpu_interrupt as u32),
);
}
Ok(())
@ -491,7 +491,7 @@ mod vectored {
map(Cpu::current(), interrupt, cpu_interrupt);
xtensa_lx::interrupt::enable_mask(
xtensa_lx::interrupt::get_mask() | 1 << cpu_interrupt as u32,
xtensa_lx::interrupt::get_mask() | (1 << cpu_interrupt as u32),
);
}
Ok(())

2
esp-hal/src/lcd_cam/lcd/i8080.rs
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@ -343,7 +343,7 @@ where
w.lcd_cmd().set_bit();
w.lcd_cmd_2_cycle_en().set_bit()
});
let cmd = first.into() as u32 | (second.into() as u32) << 16;
let cmd = first.into() as u32 | ((second.into() as u32) << 16);
self.regs()
.lcd_cmd_val()
.write(|w| unsafe { w.lcd_cmd_value().bits(cmd) });

2
esp-hal/src/soc/esp32/efuse/mod.rs
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@ -116,7 +116,7 @@ impl Efuse {
/// Returns the CHIP_VER_PKG eFuse value.
pub fn chip_type() -> ChipType {
let chip_ver = Self::read_field_le::<u8>(CHIP_PACKAGE)
| Self::read_field_le::<u8>(CHIP_PACKAGE_4BIT) << 4;
| (Self::read_field_le::<u8>(CHIP_PACKAGE_4BIT) << 4);
match chip_ver {
0 => ChipType::Esp32D0wdq6,

2
esp-hal/src/soc/esp32/gpio.rs
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@ -115,7 +115,7 @@ pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
Cpu::AppCpu => int_enable as u8 | ((nmi_enable as u8) << 1),
// this should be bits 3 & 4 respectively, according to the TRM, but it doesn't seem to
// work. This does though.
Cpu::ProCpu => (int_enable as u8) << 2 | ((nmi_enable as u8) << 3),
Cpu::ProCpu => ((int_enable as u8) << 2) | ((nmi_enable as u8) << 3),
}
}

2
esp-hal/src/soc/esp32/psram.rs
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@ -974,7 +974,7 @@ pub(crate) mod utils {
// DPORT_SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
DPORT::regs()
.host_inf_sel()
.modify(|r, w| w.bits(r.bits() | 1 << 14));
.modify(|r, w| w.bits(r.bits() | (1 << 14)));
// Start send data
spi.cmd().modify(|_, w| w.usr().set_bit());

2
esp-hal/src/soc/esp32s2/gpio.rs
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@ -121,7 +121,7 @@ pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static io_mux::GPIO0 {
pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
int_enable as u8
| ((nmi_enable as u8) << 1)
| (int_enable as u8) << 2
| ((int_enable as u8) << 2)
| ((nmi_enable as u8) << 3)
}

2
esp-hal/src/soc/esp32s2/psram.rs
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@ -238,7 +238,7 @@ pub(crate) mod utils {
const PSRAM_EID_SIZE_M: u32 = 0x07;
const PSRAM_EID_SIZE_S: u32 = 5;
let size_id = (((dev_id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S
let size_id = ((((dev_id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S)
& PSRAM_EID_SIZE_M;
const PSRAM_EID_SIZE_32MBITS: u32 = 1;

2
esp-hal/src/soc/esp32s2/trng.rs
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@ -287,7 +287,7 @@ pub(crate) fn regi2c_write_mask(block: u8, _host_id: u8, reg_add: u8, msb: u8, l
// Read the i2c bus register
let mut temp: u32 = ((block as u32 & I2C_RTC_SLAVE_ID_V as u32) << I2C_RTC_SLAVE_ID_S as u32)
| (reg_add as u32 & I2C_RTC_ADDR_V as u32) << I2C_RTC_ADDR_S as u32;
| ((reg_add as u32 & I2C_RTC_ADDR_V as u32) << I2C_RTC_ADDR_S as u32);
reg_write(I2C_RTC_CONFIG2, temp);
while reg_get_bit(I2C_RTC_CONFIG2, I2C_RTC_BUSY) != 0 {}
temp = reg_get_field(I2C_RTC_CONFIG2, I2C_RTC_DATA_S, I2C_RTC_DATA_V);

2
esp-hal/src/soc/esp32s3/psram.rs
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@ -274,7 +274,7 @@ pub(crate) mod utils {
const PSRAM_EID_SIZE_M: u32 = 0x07;
const PSRAM_EID_SIZE_S: u32 = 5;
let size_id = (((dev_id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S
let size_id = ((((dev_id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S)
& PSRAM_EID_SIZE_M;
const PSRAM_EID_SIZE_32MBITS: u32 = 1;

4
esp-hal/src/system.rs
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@ -445,7 +445,7 @@ impl PeripheralClockControl {
}
#[cfg(all(rsa, esp32))]
Peripheral::Rsa => {
peri_clk_en.modify(|r, w| unsafe { w.bits(r.bits() | (enable as u32) << 2) });
peri_clk_en.modify(|r, w| unsafe { w.bits(r.bits() | ((enable as u32) << 2)) });
}
#[cfg(all(rsa, any(esp32c3, esp32s2, esp32s3)))]
Peripheral::Rsa => {
@ -658,7 +658,7 @@ impl PeripheralClockControl {
}
#[cfg(all(rsa, esp32))]
Peripheral::Rsa => {
peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() | 1 << 2) });
peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 2)) });
peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << 2)) });
}
#[cfg(all(rsa, any(esp32c3, esp32s2, esp32s3)))]

2
esp-hal/src/time.rs
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@ -442,7 +442,7 @@ fn now() -> Instant {
};
let hi = tg0.lacthi().read().bits();
let ticks = (hi as u64) << 32u64 | lo as u64;
let ticks = ((hi as u64) << 32u64) | lo as u64;
(ticks, 16)
};

2
esp-hal/src/touch.rs
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@ -468,7 +468,7 @@ fn internal_enable_interrupt(touch_nr: u8) {
SENS::regs().sar_touch_enable().modify(|r, w| unsafe {
w.touch_pad_outen1()
.bits(r.touch_pad_outen1().bits() | 1 << touch_nr)
.bits(r.touch_pad_outen1().bits() | (1 << touch_nr))
});
}

4
esp-storage/src/esp32.rs
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@ -145,7 +145,7 @@ pub(crate) fn spiflash_write(dest_addr: u32, data: *const u32, len: u32) -> i32
let block_len = if len - block < 32 { len - block } else { 32 };
write_register(
SPI_ADDR_REG,
((dest_addr + block) & 0xffffff) | block_len << 24,
((dest_addr + block) & 0xffffff) | (block_len << 24),
);
let data_ptr = unsafe { data.offset((block / 4) as isize) };
@ -215,7 +215,7 @@ fn spiflash_wait_for_ready() {
#[link_section = ".rwtext"]
pub(crate) fn spiflash_unlock() -> i32 {
let flashchip = FLASH_CHIP_ADDR as *const EspRomSpiflashChipT;
if unsafe { (*flashchip).device_id } >> 16 & 0xff == 0x9D {
if (unsafe { (*flashchip).device_id } >> 16) & 0xff == 0x9D {
panic!("ISSI flash is not supported");
}

2
esp-wifi/src/preempt_builtin/preempt_xtensa.rs
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@ -42,7 +42,7 @@ pub(crate) fn task_create(
let stack_ptr = task_stack_ptr - (task_stack_ptr % 16);
(*ctx).trap_frame.A1 = stack_ptr as u32;
(*ctx).trap_frame.PS = 0x00040000 | (1 & 3) << 16; // For windowed ABI set WOE and CALLINC (pretend task was 'call4'd).
(*ctx).trap_frame.PS = 0x00040000 | ((1 & 3) << 16); // For windowed ABI set WOE and CALLINC (pretend task was 'call4'd).
(*ctx).trap_frame.A0 = 0;

5
esp-wifi/src/preempt_builtin/timer/xtensa.rs
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@ -35,9 +35,10 @@ pub(crate) fn setup_multitasking() {
unsafe {
let enabled = xtensa_lx::interrupt::disable();
xtensa_lx::interrupt::enable_mask(
1 << 29 // Software1
(1 << 29)
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask()
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask() | enabled,
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask()
| enabled,
);
}
}