itsscb/esp-hal
1
0
Fork 0
mirror of https://github.com/esp-rs/esp-hal.git synced 2025-09-28 04:40:52 +00:00
Code Issues Packages Projects Releases Wiki Activity

Clear LP/RTC RAM (#916)

Browse Source 
* Clear LP_RAM/RTC RAM to make sure .bss is cleared

* Rename `ulp-riscv-hal` to `esp-ulp-riscv-hal`

* CHANGELOG.md entry
This commit is contained in:
Björn Quentin 2023-11-09 14:06:58 +01:00 committed by GitHub
parent 0659928930
commit c612fecfae
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
19 changed files with 75 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
.github/workflows/ci.yml vendored
View File

@ -340,7 +340,7 @@ jobs:
- name: rustdoc - name: rustdoc
run: cd esp32h2-hal/ && cargo doc --features=eh1 run: cd esp32h2-hal/ && cargo doc --features=eh1
ulp-riscv-hal: esp-ulp-riscv-hal:
runs-on: ubuntu-latest runs-on: ubuntu-latest
steps: steps:
@ -354,11 +354,11 @@ jobs:
# Perform a full build initially to verify that the examples not only # Perform a full build initially to verify that the examples not only
# build, but also link successfully. # build, but also link successfully.
- name: build ulp-riscv-hal (esp32s3) - name: build esp-ulp-riscv-hal (esp32s3)
run: cd ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples run: cd esp-ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples
# Ensure documentation can be built # Ensure documentation can be built
- name: rustdoc - name: rustdoc
run: cd ulp-riscv-hal/ && cargo doc --features=esp32s3 run: cd esp-ulp-riscv-hal/ && cargo doc --features=esp32s3
esp32s2-hal: esp32s2-hal:
runs-on: ubuntu-latest runs-on: ubuntu-latest
@ -377,10 +377,10 @@ jobs:
components: rust-src components: rust-src
- uses: Swatinem/rust-cache@v2 - uses: Swatinem/rust-cache@v2
# build the ulp-riscv-hal examples first to make sure the examples which expect # build the esp-ulp-riscv-hal examples first to make sure the examples which expect
# the ELF files to be present will compile # the ELF files to be present will compile
- name: build ulp-riscv-hal prerequisites - name: build esp-ulp-riscv-hal prerequisites
run: cd ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s2 --examples run: cd esp-ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s2 --examples
# Perform a full build initially to verify that the examples not only # Perform a full build initially to verify that the examples not only
# build, but also link successfully. # build, but also link successfully.
@ -452,10 +452,10 @@ jobs:
components: rust-src components: rust-src
- uses: Swatinem/rust-cache@v2 - uses: Swatinem/rust-cache@v2
# build the ulp-riscv-hal examples first to make sure the examples which expect # build the esp-ulp-riscv-hal examples first to make sure the examples which expect
# the ELF files to be present will compile # the ELF files to be present will compile
- name: build ulp-riscv-hal prerequisites - name: build esp-ulp-riscv-hal prerequisites
run: cd ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples run: cd esp-ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples
# Perform a full build initially to verify that the examples not only # Perform a full build initially to verify that the examples not only
# build, but also link successfully. # build, but also link successfully.
@ -596,10 +596,10 @@ jobs:
components: rust-src components: rust-src
- uses: Swatinem/rust-cache@v2 - uses: Swatinem/rust-cache@v2
# build the ulp-riscv-hal examples first to make sure the examples which expect # build the esp-ulp-riscv-hal examples first to make sure the examples which expect
# the ELF files to be present will compile # the ELF files to be present will compile
- name: build ulp-riscv-hal prerequisites - name: build esp-ulp-riscv-hal prerequisites
run: cd ulp-riscv-hal/ && RUSTC_BOOTSTRAP=1 cargo +1.67 build --release --features=esp32s3 --examples run: cd esp-ulp-riscv-hal/ && RUSTC_BOOTSTRAP=1 cargo +1.67 build --release --features=esp32s3 --examples
# Verify the MSRV for all Xtensa chips. # Verify the MSRV for all Xtensa chips.
- name: msrv (esp32-hal) - name: msrv (esp32-hal)
@ -645,8 +645,8 @@ jobs:
run: cargo +stable clippy --manifest-path=esp32c6-lp-hal/Cargo.toml -- -D warnings -A asm-sub-register run: cargo +stable clippy --manifest-path=esp32c6-lp-hal/Cargo.toml -- -D warnings -A asm-sub-register
- name: clippy (esp32h2-hal) - name: clippy (esp32h2-hal)
run: cargo +stable clippy --manifest-path=esp32h2-hal/Cargo.toml -- -D warnings run: cargo +stable clippy --manifest-path=esp32h2-hal/Cargo.toml -- -D warnings
- name: clippy (ulp-riscv-hal) - name: clippy (esp-ulp-riscv-hal)
run: cargo +stable clippy --manifest-path=ulp-riscv-hal/Cargo.toml --features=esp32s3 -- -D warnings -A asm-sub-register run: cargo +stable clippy --manifest-path=esp-ulp-riscv-hal/Cargo.toml --features=esp32s3 -- -D warnings -A asm-sub-register
clippy-xtensa: clippy-xtensa:
runs-on: ubuntu-latest runs-on: ubuntu-latest
@ -706,5 +706,5 @@ jobs:
run: cargo fmt --all --manifest-path=esp32s2-hal/Cargo.toml -- --check run: cargo fmt --all --manifest-path=esp32s2-hal/Cargo.toml -- --check
- name: rustfmt (esp32s3-hal) - name: rustfmt (esp32s3-hal)
run: cargo fmt --all --manifest-path=esp32s3-hal/Cargo.toml -- --check run: cargo fmt --all --manifest-path=esp32s3-hal/Cargo.toml -- --check
- name: rustfmt (ulp-riscv-hal) - name: rustfmt (esp-ulp-riscv-hal)
run: cargo fmt --all --manifest-path=ulp-riscv-hal/Cargo.toml -- --check run: cargo fmt --all --manifest-path=esp-ulp-riscv-hal/Cargo.toml -- --check

1
CHANGELOG.md
View File

@ -21,6 +21,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- ESP32-C2/C3 examples: fix build error (#899) - ESP32-C2/C3 examples: fix build error (#899)
- ESP32-S3: Fix GPIO interrupt handler crashing when using GPIO48. (#898) - ESP32-S3: Fix GPIO interrupt handler crashing when using GPIO48. (#898)
- Fixed short wait times in embassy causing hangs (#906) - Fixed short wait times in embassy causing hangs (#906)
- Make sure to clear LP/RTC RAM before loading code (#916)
### Removed ### Removed

10
esp-hal-common/src/soc/esp32c6/lp_core.rs
View File

@ -109,7 +109,15 @@ impl<'d> LpCore<'d> {
}, },
} }
Self { _lp_core: lp_core } let mut this = Self { _lp_core: lp_core };
this.stop();
// clear all of LP_RAM - this makes sure .bss is cleared without relying
let lp_ram =
unsafe { core::slice::from_raw_parts_mut(0x5000_0000 as *mut u32, 16 * 1024 / 4) };
lp_ram.fill(0u32);
this
} }
/// Stop the LP core /// Stop the LP core

18
esp-hal-common/src/soc/esp32s2/ulp_core.rs
View File

@ -29,9 +29,11 @@
//! ulp_core.run(esp32s3_hal::ulp_core::UlpCoreWakeupSource::HpCpu); //! ulp_core.run(esp32s3_hal::ulp_core::UlpCoreWakeupSource::HpCpu);
//! println!("ulpcore run"); //! println!("ulpcore run");
//! //!
//! let data = (0x5000_0010 - 0) as *mut u32; //! unsafe {
//! loop { //! let data = 0x5000_0010 as *mut u32;
//! println!("Current {}", unsafe { data.read_volatile() }); //! loop {
//! println!("Current {}", unsafe { data.read_volatile() });
//! }
//! } //! }
//! ``` //! ```
use esp32s2 as pac; use esp32s2 as pac;
@ -54,11 +56,17 @@ pub struct UlpCore<'d> {
impl<'d> UlpCore<'d> { impl<'d> UlpCore<'d> {
pub fn new(lp_core: impl Peripheral<P = crate::soc::peripherals::ULP_RISCV_CORE> + 'd) -> Self { pub fn new(lp_core: impl Peripheral<P = crate::soc::peripherals::ULP_RISCV_CORE> + 'd) -> Self {
crate::into_ref!(lp_core); crate::into_ref!(lp_core);
// clear all of RTC_SLOW_RAM - this makes sure .bss is cleared without relying
let lp_ram =
unsafe { core::slice::from_raw_parts_mut(0x5000_0000 as *mut u32, 8 * 1024 / 4) };
lp_ram.fill(0u32);
Self { _lp_core: lp_core } Self { _lp_core: lp_core }
} }
// currently stopping the ULP doesn't work (while following the proсedures // currently stopping the ULP doesn't work (while following the procedures
// outlines in the TRM) - so don't offer this funtion for now // outlines in the TRM) - so don't offer this function for now
// //
// pub fn stop(&mut self) { // pub fn stop(&mut self) {
// ulp_stop(); // ulp_stop();

21
esp-hal-common/src/soc/esp32s3/ulp_core.rs
View File

@ -29,9 +29,11 @@
//! ulp_core.run(esp32s3_hal::ulp_core::UlpCoreWakeupSource::HpCpu); //! ulp_core.run(esp32s3_hal::ulp_core::UlpCoreWakeupSource::HpCpu);
//! println!("ulpcore run"); //! println!("ulpcore run");
//! //!
//! let data = (0x5000_0010 - 0) as *mut u32; //! unsafe {
//! loop { //! let data = 0x5000_0010 as *mut u32;
//! println!("Current {}", unsafe { data.read_volatile() }); //! loop {
//! println!("Current {}", unsafe { data.read_volatile() });
//! }
//! } //! }
//! ``` //! ```
@ -55,7 +57,16 @@ pub struct UlpCore<'d> {
impl<'d> UlpCore<'d> { impl<'d> UlpCore<'d> {
pub fn new(lp_core: impl Peripheral<P = crate::soc::peripherals::ULP_RISCV_CORE> + 'd) -> Self { pub fn new(lp_core: impl Peripheral<P = crate::soc::peripherals::ULP_RISCV_CORE> + 'd) -> Self {
crate::into_ref!(lp_core); crate::into_ref!(lp_core);
Self { _lp_core: lp_core }
let mut this = Self { _lp_core: lp_core };
this.stop();
// clear all of RTC_SLOW_RAM - this makes sure .bss is cleared without relying
let lp_ram =
unsafe { core::slice::from_raw_parts_mut(0x5000_0000 as *mut u32, 8 * 1024 / 4) };
lp_ram.fill(0u32);
this
} }
pub fn stop(&mut self) { pub fn stop(&mut self) {
@ -99,7 +110,7 @@ fn ulp_run(wakeup_src: UlpCoreWakeupSource) {
.cocpu_ctrl .cocpu_ctrl
.modify(|_, w| w.cocpu_shut_reset_en().set_bit()); .modify(|_, w| w.cocpu_shut_reset_en().set_bit());
// The coprocessor cpu trap signal doesnt have a stable reset value, // The coprocessor cpu trap signal doesn't have a stable reset value,
// force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU // force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU
rtc_cntl rtc_cntl
.cocpu_ctrl .cocpu_ctrl

12
esp-hal-procmacros/src/lib.rs
View File

@ -127,11 +127,11 @@ fn get_hal_crate() -> (
#[cfg(feature = "esp32s2")] #[cfg(feature = "esp32s2")]
let hal_crate = crate_name("esp32s2-hal"); let hal_crate = crate_name("esp32s2-hal");
#[cfg(feature = "esp32s2-ulp")] #[cfg(feature = "esp32s2-ulp")]
let hal_crate = crate_name("ulp-riscv-hal"); let hal_crate = crate_name("esp-ulp-riscv-hal");
#[cfg(feature = "esp32s3")] #[cfg(feature = "esp32s3")]
let hal_crate = crate_name("esp32s3-hal"); let hal_crate = crate_name("esp32s3-hal");
#[cfg(feature = "esp32s3-ulp")] #[cfg(feature = "esp32s3-ulp")]
let hal_crate = crate_name("ulp-riscv-hal"); let hal_crate = crate_name("esp-ulp-riscv-hal");
// Crate name: // Crate name:
#[cfg(feature = "esp32")] #[cfg(feature = "esp32")]
@ -149,11 +149,11 @@ fn get_hal_crate() -> (
#[cfg(feature = "esp32s2")] #[cfg(feature = "esp32s2")]
let hal_crate_name = Ident::new("esp32s2_hal", Span::call_site().into()); let hal_crate_name = Ident::new("esp32s2_hal", Span::call_site().into());
#[cfg(feature = "esp32s2-ulp")] #[cfg(feature = "esp32s2-ulp")]
let hal_crate_name = Ident::new("ulp_riscv_hal", Span::call_site().into()); let hal_crate_name = Ident::new("esp_ulp_riscv_hal", Span::call_site().into());
#[cfg(feature = "esp32s3")] #[cfg(feature = "esp32s3")]
let hal_crate_name = Ident::new("esp32s3_hal", Span::call_site().into()); let hal_crate_name = Ident::new("esp32s3_hal", Span::call_site().into());
#[cfg(feature = "esp32s3-ulp")] #[cfg(feature = "esp32s3-ulp")]
let hal_crate_name = Ident::new("ulp_riscv_hal", Span::call_site().into()); let hal_crate_name = Ident::new("esp_ulp_riscv_hal", Span::call_site().into());
(hal_crate, hal_crate_name) (hal_crate, hal_crate_name)
} }
@ -681,13 +681,13 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
crate_name("esp32c6-lp-hal").expect("esp32c6_lp_hal is present in `Cargo.toml`"); crate_name("esp32c6-lp-hal").expect("esp32c6_lp_hal is present in `Cargo.toml`");
#[cfg(any(feature = "esp32s2-ulp", feature = "esp32s3-ulp"))] #[cfg(any(feature = "esp32s2-ulp", feature = "esp32s3-ulp"))]
let found_crate = let found_crate =
crate_name("ulp-riscv-hal").expect("ulp-riscv-hal is present in `Cargo.toml`"); crate_name("esp-ulp-riscv-hal").expect("esp-ulp-riscv-hal is present in `Cargo.toml`");
let hal_crate = match found_crate { let hal_crate = match found_crate {
#[cfg(feature = "esp32c6-lp")] #[cfg(feature = "esp32c6-lp")]
FoundCrate::Itself => quote!(esp32c6_lp_hal), FoundCrate::Itself => quote!(esp32c6_lp_hal),
#[cfg(any(feature = "esp32s2-ulp", feature = "esp32s3-ulp"))] #[cfg(any(feature = "esp32s2-ulp", feature = "esp32s3-ulp"))]
FoundCrate::Itself => quote!(ulp_riscv_hal), FoundCrate::Itself => quote!(esp_ulp_riscv_hal),
FoundCrate::Name(name) => { FoundCrate::Name(name) => {
let ident = Ident::new(&name, Span::call_site()); let ident = Ident::new(&name, Span::call_site());
quote!( #ident::Something ) quote!( #ident::Something )

0
ulp-riscv-hal/.cargo/config.toml → esp-ulp-riscv-hal/.cargo/config.toml
View File

8
ulp-riscv-hal/CHANGELOG.md → esp-ulp-riscv-hal/CHANGELOG.md
View File

@ -9,14 +9,14 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
### Added ### Added
- Add the `esp32c6-lp-hal` package (#714) - Add the `ulp-riscv-hal` package (#840)
- Add GPIO (output) and delay functionality to `esp32c6-lp-hal` (#715)
- Add GPIO input support and implement additional `embedded-hal` output traits for the C6's LP core [#720]
### Changed ### Changed
- Renamed to `esp-ulp-riscv-hal` (#916)
### Fixed ### Fixed
### Removed ### Removed
[Unreleased]: https://github.com/esp-rs/esp-hal/commits/main/esp32c6-lp-hal [Unreleased]: https://github.com/esp-rs/esp-hal/commits/main/esp-ulp-riscv-hal

2
ulp-riscv-hal/Cargo.toml → esp-ulp-riscv-hal/Cargo.toml
View File

@ -1,5 +1,5 @@
[package] [package]
name = "ulp-riscv-hal" name = "esp-ulp-riscv-hal"
version = "0.1.0" version = "0.1.0"
edition = "2021" edition = "2021"
rust-version = "1.67.0" rust-version = "1.67.0"

8
ulp-riscv-hal/README.md → esp-ulp-riscv-hal/README.md
View File

@ -1,8 +1,8 @@
# ulp-lp-hal # ulp-lp-hal
[![Crates.io](https://img.shields.io/crates/v/ulp-lp-hal?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/ulp-lp-hal) [![Crates.io](https://img.shields.io/crates/v/esp-ulp-lp-hal?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-ulp-lp-hal)
[![docs.rs](https://img.shields.io/docsrs/ulp-lp-hal?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/ulp-lp-hal) [![docs.rs](https://img.shields.io/docsrs/esp-ulp-lp-hal?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-ulp-lp-hal)
![Crates.io](https://img.shields.io/crates/l/ulp-lp-hal?labelColor=1C2C2E&style=flat-square) ![Crates.io](https://img.shields.io/crates/l/esp-ulp-lp-hal?labelColor=1C2C2E&style=flat-square)
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org) [![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
`no_std` HAL for the ESP32-S2/ESP32-S3 from Espressif's ultra-low-power coprocessor. `no_std` HAL for the ESP32-S2/ESP32-S3 from Espressif's ultra-low-power coprocessor.
@ -15,7 +15,7 @@ Please refer to the documentation for more information.
## [Documentation] ## [Documentation]
[documentation]: https://docs.rs/ulp-lp-hal/ [documentation]: https://docs.rs/esp-ulp-lp-hal/
## Resources ## Resources

0
ulp-riscv-hal/build.rs → esp-ulp-riscv-hal/build.rs
View File

4
ulp-riscv-hal/examples/blinky.rs → esp-ulp-riscv-hal/examples/blinky.rs
View File

@ -6,12 +6,12 @@
#![no_std] #![no_std]
#![no_main] #![no_main]
use panic_halt as _; use esp_ulp_riscv_hal::{
use ulp_riscv_hal::{
delay::Delay, delay::Delay,
gpio::{GpioPin, Output, PushPull}, gpio::{GpioPin, Output, PushPull},
prelude::*, prelude::*,
}; };
use panic_halt as _;
#[entry] #[entry]
fn main(mut gpio1: GpioPin<Output<PushPull>, 1>) -> ! { fn main(mut gpio1: GpioPin<Output<PushPull>, 1>) -> ! {

0
ulp-riscv-hal/ld/link.x → esp-ulp-riscv-hal/ld/link.x
View File

0
ulp-riscv-hal/src/delay.rs → esp-ulp-riscv-hal/src/delay.rs
View File

0
ulp-riscv-hal/src/gpio.rs → esp-ulp-riscv-hal/src/gpio.rs
View File

0
ulp-riscv-hal/src/lib.rs → esp-ulp-riscv-hal/src/lib.rs
View File

0
ulp-riscv-hal/src/prelude.rs → esp-ulp-riscv-hal/src/prelude.rs
View File

2
esp32s2-hal/examples/ulp_riscv_core_basic.rs
View File

@ -30,7 +30,7 @@ fn main() -> ! {
// load code to LP core // load code to LP core
let lp_core_code = load_lp_code!( let lp_core_code = load_lp_code!(
"../ulp-riscv-hal/target/riscv32imc-unknown-none-elf/release/examples/blinky" "../esp-ulp-riscv-hal/target/riscv32imc-unknown-none-elf/release/examples/blinky"
); );
// start LP core // start LP core

2
esp32s3-hal/examples/ulp_riscv_core_basic.rs
View File

@ -32,7 +32,7 @@ fn main() -> ! {
// load code to LP core // load code to LP core
let lp_core_code = load_lp_code!( let lp_core_code = load_lp_code!(
"../ulp-riscv-hal/target/riscv32imc-unknown-none-elf/release/examples/blinky" "../esp-ulp-riscv-hal/target/riscv32imc-unknown-none-elf/release/examples/blinky"
); );
// start LP core // start LP core