mirror of
https://github.com/esp-rs/esp-hal.git
synced 2026-05-03 20:45:46 +00:00
Riscv stable CI (#1491)
* Remove interrupt and thread executor embassy features * Reserve sw interrupt 3 (4) instead of 0 for multicore systems with the embassy feature enabled * Add thread mode context id and fix up examples * Use stable rust for riscv CI * Add binary-logs feature to 8021504 driver * Add binary-logs feature to 8021504 driver
This commit is contained in:
18
.github/workflows/ci.yml
vendored
18
.github/workflows/ci.yml
vendored
@@ -71,7 +71,7 @@ jobs:
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uses: dtolnay/rust-toolchain@v1
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with:
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target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
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toolchain: nightly
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toolchain: stable
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components: rust-src
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# Install the Rust toolchain for Xtensa devices:
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- if: contains(fromJson('["esp32", "esp32s2", "esp32s3"]'), matrix.device.soc)
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@@ -119,7 +119,7 @@ jobs:
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- uses: dtolnay/rust-toolchain@v1
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with:
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target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
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toolchain: nightly
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toolchain: stable
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components: rust-src
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- uses: Swatinem/rust-cache@v2
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@@ -139,24 +139,24 @@ jobs:
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- uses: dtolnay/rust-toolchain@v1
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with:
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target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
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toolchain: nightly
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toolchain: stable
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components: rust-src
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- uses: Swatinem/rust-cache@v2
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# Build for all RISC-V targets (no features):
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- name: Build esp-riscv-rt (riscv32imc, no features)
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run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imc-unknown-none-elf
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run: cd esp-riscv-rt/ && cargo build --target=riscv32imc-unknown-none-elf
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- name: Build esp-riscv-rt (riscv32imac, no features)
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run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imac-unknown-none-elf
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run: cd esp-riscv-rt/ && cargo build --target=riscv32imac-unknown-none-elf
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- name: Build esp-riscv-rt (riscv32imafc, no features)
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run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imafc-unknown-none-elf
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run: cd esp-riscv-rt/ && cargo build --target=riscv32imafc-unknown-none-elf
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# Build for all RISC-V targets (all features):
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- name: Build esp-riscv-rt (riscv32imc, all features)
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run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imc-unknown-none-elf --features=ci
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run: cd esp-riscv-rt/ && cargo build --target=riscv32imc-unknown-none-elf --features=ci
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- name: Build esp-riscv-rt (riscv32imac, all features)
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run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imac-unknown-none-elf --features=ci
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run: cd esp-riscv-rt/ && cargo build --target=riscv32imac-unknown-none-elf --features=ci
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- name: Build esp-riscv-rt (riscv32imafc, all features)
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run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imafc-unknown-none-elf --features=ci
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run: cd esp-riscv-rt/ && cargo build --target=riscv32imafc-unknown-none-elf --features=ci
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# Ensure documentation can be built
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- name: rustdoc
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run: cd esp-riscv-rt/ && cargo doc
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@@ -29,3 +29,6 @@ vcell = "0.1.3"
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default = []
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esp32c6 = ["esp-hal/esp32c6", "esp-wifi-sys/esp32c6"]
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esp32h2 = ["esp-hal/esp32h2", "esp-wifi-sys/esp32h2"]
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## Output logging from the phy blobs. Requires nightly
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binary-logs = []
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@@ -1,39 +1,44 @@
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use core::{ffi::VaListImpl, fmt::Write};
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use log::info;
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use self::str_buf::StrBuf;
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#[cfg(feature = "binary-logs")]
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mod str_buf;
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#[no_mangle]
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pub unsafe extern "C" fn phy_printf(format: *const u8, args: ...) {
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syslog(format, args);
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}
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#[cfg(feature = "binary-logs")]
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mod binary_logs {
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use core::{ffi::VaListImpl, fmt::Write};
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#[no_mangle]
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pub unsafe extern "C" fn rtc_printf(format: *const u8, args: ...) {
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syslog(format, args);
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}
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use log::info;
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#[no_mangle]
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pub unsafe extern "C" fn coexist_printf(format: *const u8, args: ...) {
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syslog(format, args);
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}
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use super::str_buf::StrBuf;
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pub unsafe extern "C" fn syslog(format: *const u8, args: VaListImpl) {
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#[no_mangle]
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pub unsafe extern "C" fn phy_printf(_format: *const u8, _args: ...) {
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syslog(_format, _args);
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}
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#[no_mangle]
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pub unsafe extern "C" fn rtc_printf(_format: *const u8, _args: ...) {
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#[cfg(feature = "binary-logs")]
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syslog(_format, _args);
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}
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#[no_mangle]
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pub unsafe extern "C" fn coexist_printf(_format: *const u8, _args: ...) {
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#[cfg(feature = "binary-logs")]
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syslog(_format, _args);
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}
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pub unsafe extern "C" fn syslog(format: *const u8, args: VaListImpl) {
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let mut buf = [0u8; 512];
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vsnprintf(&mut buf as *mut u8, 511, format, args);
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let res_str = StrBuf::from(&buf as *const u8);
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info!("{}", res_str.as_str_ref());
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}
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}
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pub(crate) unsafe fn vsnprintf(
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pub(crate) unsafe fn vsnprintf(
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dst: *mut u8,
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_n: u32,
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format: *const u8,
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mut args: VaListImpl,
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) -> i32 {
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) -> i32 {
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let fmt_str_ptr = format;
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let mut res_str = StrBuf::new();
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@@ -127,4 +132,15 @@ pub(crate) unsafe fn vsnprintf(
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*(dst.offset(idx)) = 0;
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idx as i32
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}
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}
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#[cfg(not(feature = "binary-logs"))]
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mod dummy {
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#[no_mangle]
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pub unsafe extern "C" fn phy_printf(_format: *const u8, _args: *const ()) {}
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#[no_mangle]
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pub unsafe extern "C" fn rtc_printf(_format: *const u8, _args: *const ()) {}
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#[no_mangle]
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pub unsafe extern "C" fn coexist_printf(_format: *const u8, _args: *const ()) {}
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}
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@@ -6,7 +6,7 @@
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//! [IEEE 802.15.4]: https://en.wikipedia.org/wiki/IEEE_802.15.4
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#![no_std]
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#![feature(c_variadic)]
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#![cfg_attr(feature = "binary-logs", feature(c_variadic))]
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use core::{cell::RefCell, marker::PhantomData};
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@@ -16,7 +16,6 @@
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use embassy_executor::Spawner;
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use embassy_time::{Duration, Timer};
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@@ -28,7 +28,6 @@
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#![no_std]
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#![no_main]
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#![feature(asm_experimental_arch)]
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use esp_backtrace as _;
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use esp_hal::{
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@@ -21,6 +21,7 @@ pub enum Package {
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EspHal,
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EspHalProcmacros,
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EspHalSmartled,
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EspIeee802154,
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EspLpHal,
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EspRiscvRt,
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Examples,
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@@ -158,7 +159,6 @@ pub fn build_documentation(
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// Build up an array of command-line arguments to pass to `cargo`:
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let mut builder = CargoArgsBuilder::default()
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.subcommand("doc")
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.arg("-Zbuild-std=core") // Required for Xtensa, for some reason
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.target(target)
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.features(&features);
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@@ -169,6 +169,7 @@ pub fn build_documentation(
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// If targeting an Xtensa device, we must use the '+esp' toolchain modifier:
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if target.starts_with("xtensa") {
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builder = builder.toolchain("esp");
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builder = builder.arg("-Zbuild-std=core,alloc")
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}
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let args = builder.build();
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@@ -270,7 +271,6 @@ pub fn execute_app(
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let mut builder = CargoArgsBuilder::default()
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.subcommand(subcommand)
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.arg("-Zbuild-std=alloc,core")
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.arg("--release")
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.target(target)
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.features(&features)
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@@ -289,6 +289,7 @@ pub fn execute_app(
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// If targeting an Xtensa device, we must use the '+esp' toolchain modifier:
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if target.starts_with("xtensa") {
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builder = builder.toolchain("esp");
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builder = builder.arg("-Zbuild-std=core,alloc")
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}
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let args = builder.build();
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@@ -316,7 +317,6 @@ pub fn build_package(
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let mut builder = CargoArgsBuilder::default()
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.subcommand("build")
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.arg("-Zbuild-std=core")
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.arg("--release");
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if let Some(toolchain) = toolchain {
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@@ -324,6 +324,11 @@ pub fn build_package(
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}
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if let Some(target) = target {
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// If targeting an Xtensa device, we must use the '+esp' toolchain modifier:
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if target.starts_with("xtensa") {
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builder = builder.toolchain("esp");
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builder = builder.arg("-Zbuild-std=core,alloc")
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}
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builder = builder.target(target);
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}
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