2 Commits

Author SHA1 Message Date
Jesse Braham
a92c46f309 Correct a number of comments in various examples 2023-05-25 06:02:15 -07:00
onsdagens
fe84e74151
Adding priority based interrupt preemption (#448)
* Software interrupt support added, not sure if the code is good

* Added support for remaining SW interrupts

* Added support for remaining SW interrupts

* Added support for remaining SW interrupts

* Added support for esp32c2, esp32s2, esp32s3

* Added support for esp32c2, esp32s2, esp32s3

* Added support for esp32c2, esp32s2, esp32s3

* Added support for esp32c2, esp32s2, esp32s3

* Software interrupt example for esp32c3

* Added support for esp32c2, esp32s2, esp32s3

* Software interrupt example for esp32c3

* prio based preemption only, vector table reverted

* prio based preemption only, vector table reverted

* fixed a rare bug causing misaligned memory accesses

* fixed a rare bug causing misaligned memory accesses

* fixed a rare bug causing misaligned memory accesses

* fixed rare bug causing misaligned memory access when emulating atomics

* fixed a rare bug causing misaligned memory accesses

* fixed a rare bug causing misaligned memory accesses

* broke something

* broke something

* fixed alignment bug

* Tentative: added support for interrupt preemption without involving the rt

* Added feature enabling priority based interrupt preemption

* Fixed failed merge

* Tagged preemption helpers with inline always

* Disable interrupts before restoring context to avoid ruining it

* Fix max priority edge case

* Fix broken merge

* Added examples for the remaining RISC-V ESPs

* Update esp-hal-common/src/interrupt/riscv.rs

Co-authored-by: sethp <seth.pellegrino@gmail.com>

* Update esp32c2-hal/examples/interrupt_preemption.rs

Co-authored-by: sethp <seth.pellegrino@gmail.com>

* Update esp-hal-common/src/interrupt/riscv.rs

Co-authored-by: sethp <seth.pellegrino@gmail.com>

* Example comments courtesy of @sethp

* Reverted irrelevant changes, raised high prio interrupt to max prio

* Rolling back an irrelevant change

* Rolling back an irrelevant change

* Update esp-hal-common/src/interrupt/riscv.rs

Co-authored-by: Scott Mabin <scott@mabez.dev>

* Update esp-hal-common/src/interrupt/riscv.rs

Co-authored-by: Scott Mabin <scott@mabez.dev>

* Moved imports to avoid warnings, moved functions to ram, moved interrupt disable to before prio threshold is restored

* Added preemption for the ESP32C6

* Moved helper functions into the relevant modules, changed threshold for ESP32C6 to machine mode one

* ESP32C6 Threshold register changed to machine mode one, corrected threshold set.

---------

Co-authored-by: sethp <seth.pellegrino@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
2023-05-05 11:40:54 +01:00