* New package releases
* Fix the `CHANGELOG.md` check in CI
* `defmt` is annoying
* Update documentation index to point to new version, correct release date
* Remove docs.rs badge from and update docs link in `README.md`
* Silence `clippy`
* Fix documentation link in `esp-hal/README.md`
* Remove the chip-specific HAL packages
* Update some doc comments which were missed, fix build script for ESP32/S2
* Refactor/update `esp-hal-procmacros`
* Create the `examples` package, add back all of the previously existing examples
* Use `xtask` automation package for checking examples and documentation in CI
* Combine the `rt-riscv` and `rt-xtensa` features into a single `rt` feature
* Bump MSRV to 1.76.0 (shocking!)
* Re-document the features for the HAL
* No need to re-export the `riscv` package like this
* Make clippy happy, improve CI clippy checks
* Update `CHANGELOG.md`
* riscv: zero bss
Co-authored-by: Björn Quentin <bjoernQ@users.noreply.github.com>
* Address a number of review comments
* Correct pin number in `hello_rgb` example for ESP32-C3
* Address the remaining review comments
* More small tweaks/improvements
* Fix RMT examples (#11)
* Fix RMT examples
* Remove logger-init
* Make I2S examples work on ESP32 (#12)
* Make I2S examples work on ESP32
* Remove logger init
* Fix the direct-vectoring examples on all RISCV chips (#10)
* Update GPIOs for some examples...
* Embassy timer example fixes (#13)
* Switch to generic queue instead of integrated for all examples
* changelog
* Update GPIO in another example, make `rustfmt` happy
* Fix ESP32-S2 PSRAM
* Avoid UART0 and SPI flash pins (#15)
* Avoid UART0 and SPI flash pins
* Fix spi_eh1_device_loopback for non-ESP32
* Update examples/src/bin/gpio_interrupt.rs
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
---------
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
---------
Co-authored-by: Scott Mabin <scott@mabez.dev>
Co-authored-by: Björn Quentin <bjoernQ@users.noreply.github.com>
Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
* Bump MSRV to 1.67, check with `defmt` feature enabled in MSRV checks where applicable
* Add `esp32c6-lp-hal-procmacros` package to VS Code workspace
* Update `CHANGELOG.md`
* Macro to load LP core code
* Fix imports, add CHANGELOG.md entry
* Avoid code warning
* Omit path from function signature
* More error checking
* Clippy fix
* Include the ELF used by the lp_core_basic example
* Make object dependency optional
* Use 1.65 for RISCV MSRV check
* Use RUSTC_BOOTSTRAP for RISCV MSRV check
* Remove the pre-compiled LP core example
* Pin toml_edit in esp32c6-lp-hal-procmacro
* Add README, improve documentation for `esp-hal-procmacros`
* Improve documentation for `esp-hal-smartled`
* Use esp-rs logo for all packages' documentation
* Add additional `cfg` gates to re-exports in `esp-hal-common`
This leaves only `clock`, `delay`, `peripheral`, `prelude`, `rom`, and `soc` *not* behind `cfg`s
* Simplify the prelude, update its `cfg`s, and re-export some missing traits
* Update various dependencies
* Create the `esp32c6-hal` package
* Teach `esp-hal-common` about the ESP32-C6
* Get a number of peripheral drivers building for the ESP32-C6
bckup
initial clocks_ii
* Create the `esp32c6-hal` package
C6: update
* Simplify and fix the linker script
update
* C6: add I2S
* Create the `esp32c6-hal` package
* Teach `esp-hal-common` about the ESP32-C6
* Get a number of peripheral drivers building for the ESP32-C6
bckup
initial clocks_ii
* Create the `esp32c6-hal` package
* C6: update
* Simplify and fix the linker script
* update
* C6: add I2S
* update
* C6 Interrupts
* C6: Update build.rs, linker scripts and initial examples
* C6: RMT
* Fix interrupt handling
* Fix `ClockControl::configure`
* C6: revert to I2S0 instead of just I2S
* C6: rebase and update
* RTC not buildable
* Implement RWDT and SWD disable
* C6: working LEDC
* C6: working RMT
* C6: add aes
* C6: add mcpwm
* C6: add rtc_cntln - not finished
* C6: update and formatting
* C6: add pcnt
* C6: add examples and format
* Remove inline assembly, fix interrupts and linker scripts
* Remove unused features, update cargo config for atomic emu, misc cleanup
* Get ADC building and example "working" (as much as it ever does)
* Remove a bunch of unused constants which were copied from ESP-IDF
* The `mcpwm` example now works correctly
* Get `TWAI` peripheral driver building for C6
* Clean up the `rtc_cntl` module and get all the other HALs building again
* Add the C6 to our CI workflow
* Fix various things that have been missed when rebasing
Still missing a few examples (`clock_monitor`, `embassy_spi`, `ram`)
* C6: Small updates in wdt (#1)
* C6: Update WDT
* C6: Update examples with WDT update
* Update `esp-println` dependency to fix build errors
* Fix formatting issues causing pre-commit hook to fail
* Get some more examples working
* Working `ram` example
* Sync with changes in `main` after rebasing
* Working `embassy_spi` example
* Use a git dependency for the PAC until we publish a release
* Fix I2S for ESP32-C6
* Fix esp32c6 direct boot (#4)
* Add direct boot support for C6
* Fix direct boot for c6
- Actually copy into rtc ram
- remove dummy section that is no longer needed (was just a waste of
flash space)
- Move RTC stuff before the no load sections
* Update RWDT and refactor RTC (#3)
* C6: Update RWDT and add example, refactor RTC and add not-really-good example
* Update based on review comments, resolve bunch of warnings and run cargo fmt
* Update C6 esp-pacs rev commit
* Fix clocks_ll/esp32c6.rs
* Fix riscv interrupts
* Remove clock_monitor example for now
* RAM example works in direct-boot mode
* Add a TODO for &mut TIMG0 and cargo fmt
* Fix linker script after a bad rebase
* Update CI and Cargo.toml embassy required features
* use riscv32imac-unknown-none-elf target for C6 in CI
* change default target to riscv32imac-unknown-none-elf
* add riscv32imac-unknown-none-elf target to MSRV job
* another cleanup
---------
Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Jesse Braham <jesse@beta7.io>
* Make required changes to include new `RADIO` peripheral
* Use published versions of PAC and `esp-println`
* Use the correct target extensions (`imac`)
* Fix the super watchdog timer, plus a few more examples
* Fix UART clock configuration
* Make sure to sync UART registers when configuring AT cmd detection
* Disable APM in direct-boot mode
* Address a number of review comments
* Fix `SPI` clocks and `rtc_watchdog` example (#6)
* fix SPI clocks
* run cargo fmt
* Add comment about used default clk src
* Fix rtc_watchdog example in BL mode
* run cargo fmt
* Update rtc_watchdog example that it works in DB mode
* README and example fixes/cleanup
* Add I2C peripheral enable and reset
* Fix `ApbSarAdc` configuration in `system.rs`
---------
Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Add the `rust-version` key to each Cargo manifest
* Normalize dependencies and features in each Cargo manifest
* Enable all features in CI when checking examples
* Update the top-level README
* Xtensa interrupt vectoring: peripheral source
- Initial Xtensa vectoring, updated esp32 gpio example to use new interrupt macro.
- Only peripheral sources supported.
- Only level one priority supported.
- CPU & Edge interrupts still need to be handled.
* Xtensa interrupt vectoring: CPU & EDGE
- Add support for handling CPU interrupts and edge interrupts
- PR required to xtensa-lx-rt for CPU handlers
* Xtensa interrupt vectoring: Priority
- Finally implement priortization
- Only three priorities available at the moment. Xtensa programmer guide
discourages using highpri interrupts in Rust/C. Guide also mentions
using software priortization to increase the number of Priorities
available
* support CPU interrupts, using patch xtensa-lx-rt
* Update example
* Add support & examples for the s2 & s3 too
* Fix formatting and missing imports
* Run interrupt handling in ram, optionally run the vector handler in ram in the examples
* Use xtensa_lx::Mutex CS when enabling interrupts
* Run clippy on each target
* Remove redundant features
* Fix C3 builds
* make enable unsafe. Add note about preallocated interrupts in vectored mode.
* Remove `INTERRUPT_LEVELS` static
The interrupt levels static introduces a few issues
- A lock is needed when configuring interrupts to keep
INTERRUPT_LEVELS in a consistent state
- Interrupts enabled from outside the Rust domain wouldn't be
serviced, this is the case with the wifi blobs
To remove it, the prioty configuration is now calculated dynamically in
the interrupt handler. Essentially INTERRUPT_LEVELS is now created once
the interrupt triggers. It has some benefits, such as only having to
look at interrupts configured on the current core, not both, but there
is of course an overhead with doing this in the interrupt.
* Allow raw interrupts on levels 4-7, whilst also supporting vectoring on levels 1-3
* rename core number features
* Fix examples and formatting
* use xtensa-lx-rt release, update pacs
* Support passing the trap frame into interrupt handlers
* cfg away the #[interrupt] macro when not using vectoring
* rename enable to map
move vectored feature to chip specific hals
* export vectored functions
- rename `enable_with_priority` to `enable`
- add docs for interrupt macro
* Update all examples to use vectored interrupts
