* adc_cal: c2: Add efuse functions for reading calibration
* adc_cal: c3: Add efuse functions for reading calibration
* adc_cal: c6: Add efuse functions for reading calibration
* adc_cal: Add extra traits to support calibration
- `AdcCalScheme<ADCI>` implemented for each calibration scheme (basic, linear, curved)
- `AdcCalEfuse` implemented for each ADC unit to get calibration data from efuse bits
* adc_cal: Add basic ADC calibration scheme
Basic calibration is related to setting some initial bias value to ADC unit.
Such values usually is stored in efuse bit fields but also can be measured
in runtime by connecting ADC input to ground internally.
* adc_cal: Add line fitting ADC calibration scheme
This scheme also includes basic calibration and implements gain correction based
on reference point.
Reference point is a pair of reference voltage and corresponding mean raw ADC
value. Such raw values usually is stored in efuse bit fields for each supported
attenuation.
Possibly it also can be measured in runtime by connecting ADC to reference
voltage internally.
* adc_cal: Add curve fitting ADC calibration scheme
This scheme also includes basic and linear and implements final polynomial error
correction.
* adc_cal: riscv: Add ADC calibration implementation for riscv chips
* adc_cal: c2: Add calibrated ADC reading example
This example uses line fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: c3: Add calibrated ADC reading example
This example uses curve fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: c6: Add calibrated ADC reading example
This example uses curve fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: riscv: Add changelog entry for ADC calibration
* Introduce a trait for DMA channels
This trait is then used to hold types related to the particular DMA channel. This change allows us to simplify user-facing types.
* Remove private type from I2s
* Remove redundant spi3 example, update examples
* Merge markdown sections
* Add changelog entry
* Add ROM MD5 definitions in linker and devices
* Add initial MD5 support
* Implement traits and add comments to MD5 module
* Add MD5 example to ESP32-C3
* Test MD5 context on the quick brown fox
* Implemenr From<Context> for Digest
* Add MD5 to the rest of the examples
* Add docs for MD5
* Remove #[repr(transparent)] from md5::Digest
* Update CHANGELOG.md
* Create issue_handler.yml
* No longer re-export `embedded-hal`, hide exported macros in documentation
* Add simple package-level documentation for each HAL package
* Clean up/simplify re-exports
* Fix the examples that I broke
* Ensure top-level modules/types/functions have doc comments
* Update CHANGELOG
* Re-export the `soc::psram` module where available
---------
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
* feat: relocate riscv isr to iram
Previously, the trap vector itself and its immediate callees
(`_start_trap` and `_start_trap_rust_hal`) were located in the mapped
instruction flash range `0x420..`, increasing cache pressure and adding
variable latency to the very beginning of the interrupt/exception
service flow.
This change places those routines in iram directly:
```
Num: Value Size Type Bind Vis Ndx Name
48177: 40380280 2428 FUNC GLOBAL DEFAULT 6 _start_trap_rust_hal
48197: 40380bfc 54 FUNC GLOBAL DEFAULT 6 _start_trap_rust
48265: 40380200 0 FUNC GLOBAL DEFAULT 6 _vector_table
48349: 40380100 0 NOTYPE GLOBAL DEFAULT 6 default_start_trap
48350: 40380100 0 NOTYPE GLOBAL DEFAULT 6 _start_trap
```
As seen via `readelf -W -s -C ./target/riscv32imc-unknown-none-elf/debug/examples/gpio_interrupt | grep -E _start_trap\|_vector\|Ndx`
* feat(riscv): place .trap in RAM
This change follows through on relocating the `_vector_table`,
`_start_trap`, and `_start_trap_rust` functions for all present
build/link modes for the 'c2, 'c3, 'c6, and 'h2.
It has been tested by running the `software_interrupts` example for the
'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to
identify how to run the `mcu-boot` mode for the 'c3, nor do I have
present access to any of the other devices for testing.
* docs: Update CHANGELOG.md
For now, only the -c3.
---
Open up LEDC fade support to all chips.
The C6 chip needs some special handling because its fade registers also
handle gamma, and the ESP chip needs some special handling because it
has two banks of channels. The code to handle these is already present
in channel.rs, but needs to be copied and adapted. Do that, and drop
all the esp32c3 feature checks.
---
Add a function to poll the duty-fade state
Use the unmasked interrupt bit in the LEDC register block, since that
will get updated by the hardware whether or not we've connected anything
to the interrupt source. Also be sure to clear that bit before starting
a new fade, so it's always clear while fading.
This will allow dumb (non-async-code) polling of the fade state after
one is started by the start_duty_fade API.
---
Fix non-C3 devices to use the right int_raw bits
These are inconsistently named between the esp32 variants.
---
Add examples of hardware duty-cycle fading
Just a relatively simple zero to 100 and back to zero, over a total of 2
seconds, to get a breathing effect.
This does make the main loop{} have a 2-second period instead of the
current nearly-zero period, but nothing else is happening so that's
fine.
---
Fix two bugs in hardware fading
When figuring out how many duty-cycle changes need to happen per counter
overflow, we need to use the absolute value of the difference between
the start and end duty values, not the raw difference. When fading from
(e.g.) 100% to 0, this will overflow, and both the debug-mode panic and
the release-mode wrapping behavior give the wrong delta value.
So calculate an absolute value difference first, and use that.
Then, when running through the while loop that allocates bits between
pwm_cycles and duty_cycle, the check on pwm_cycles was wrong -- since
the value reduces each time through the loop, we need to keep looping as
long as it's *above* some threshold, not below.
---
Simplify and refactor duty-cycle fade code
I'm not sure if this will fix the extremely-short fade times that we're
seeing with the older code, but we'll see.
Move all the calculations out of the ChannelHW implementations, and make
those *just* set registers. The calculations are the same for all chip
variants, so don't need to be duplicated for each chip feature, like the
register macros are.
Change the calculations from a loop doing bit shifts, to an explicit
division and a couple of range checks. This way we can get a lot closer
to the requested percentages and durations.
Use the u32::abs_diff function instead of open-coding it (now that I see
it exists).
Use u16::try_from() to limit the range of values, and use try_into<u16>
and map_err and the ? operator to more clearly handle numbers out of
range.
Drop the Result<> return type from the ChannelHW function, as it can't
fail anymore.
Fix the duty_range value -- before, when duty_exp was (say) 8,
duty_range would be 256, and if one of the *_duty_pct values was 100,
the start or end duty value would be too big. The range of start and
end duty values is 0..255, so we have to subtract one to handle 100%.
Finally, add a comment on the is_duty_fade_running{,_hw} methods.
---
Some fades can't work; return errors for them.
Add a new Error enum value with a sub-error enum with more details.
Return it from the error cases in the fade method.
If the calculated cycles_per_step is more than 10 bits, fail as well;
the field in the register is only 10 bits wide.
Fix all the examples to run a 1-second fade instead of a 2-second, since
the 2-second fade will run into this error. (Assert that, as well.)
---
When fading on a -c6 chip, set two more registers
The gamma functionality of -c6 chips needs two more fields set. One
tells the chip how many gamma stages it should iterate through, but we
only implement linear fading, so always use 1. The other tells the chip
to latch the value of the other gamma registers into the chosen slot, so
even though its value never changes, the write needs to happen.
---
Add changelog entry
* Small refactor to extract functions for setting up reads/writes
* Implement async capabilities for `I2C` driver
* Add async I2C examples for each supported chip
* Update CHANGELOG
* implement fetching the rtc timer value in miliseconds and mircroseconds
* fmt cleanup
* add rtc_time examples
* get_time_raw/esp32: delay 1us between time update checks like esp-idf
* cargo fmt
* Initial async_{write|flush} implementations
- ESP32C3 + UART0 example
* Support UART1 & UART2
* Add examples for all chips
* reduce number of wakers depending on uart count
* Software interrupt support added, not sure if the code is good
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* prio based preemption only, vector table reverted
* prio based preemption only, vector table reverted
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed rare bug causing misaligned memory access when emulating atomics
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* broke something
* broke something
* fixed alignment bug
* Tentative: added support for interrupt preemption without involving the rt
* Added feature enabling priority based interrupt preemption
* Fixed failed merge
* Tagged preemption helpers with inline always
* Disable interrupts before restoring context to avoid ruining it
* Fix max priority edge case
* Fix broken merge
* Added examples for the remaining RISC-V ESPs
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp32c2-hal/examples/interrupt_preemption.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Example comments courtesy of @sethp
* Reverted irrelevant changes, raised high prio interrupt to max prio
* Rolling back an irrelevant change
* Rolling back an irrelevant change
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Moved imports to avoid warnings, moved functions to ram, moved interrupt disable to before prio threshold is restored
* Added preemption for the ESP32C6
* Moved helper functions into the relevant modules, changed threshold for ESP32C6 to machine mode one
* ESP32C6 Threshold register changed to machine mode one, corrected threshold set.
---------
Co-authored-by: sethp <seth.pellegrino@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update `embedded-hal-1` and `embedded-hal-nb` dependencies to latest versions
* Update the `Delay` and `I2c` trait implementations
* Update the `SpiDevice` trait, implement `SpiDeviceRead` and `SpiDeviceWrite`
* Add README, improve documentation for `esp-hal-procmacros`
* Improve documentation for `esp-hal-smartled`
* Use esp-rs logo for all packages' documentation
