12 Commits

Author SHA1 Message Date
Jesse Braham
d12a3dbac5
Update all examples to remove unnecessary disabling of watchdogs (#768)
* Update `esp32-hal` examples

* Update `esp32c2-hal` examples

* Update `esp32c3-hal` examples

* Update `esp32c6-hal` examples

* Update `esp32h2-hal` examples

* Update `esp32s2-hal` examples

* Update `esp32s3-hal` examples

* Fix the `ram.rs` examples
2023-08-31 07:17:12 -07:00
Alex Johnson
debe2b8004
fixed async read w/o at_cmd (#652)
* fixed async read w/o at_cmd

* configurtion checks  for async `read`

* remove fifo thrhd check
2023-07-25 12:19:59 +01:00
Juraj Sadel
40bf086a0c
Add PeripheralClockControl argument to timg, wdt, sha, usb-serial-jtag and uart constructors (#463)
* PeripheralClockControl timer

* Add PeripheralClockControl to timg, wdt, sha, usb-serial-jtag and uart

* ESP32 updated examples

* ESP32C2 updated examples

* ESP32C3 updated examples

* ESP32S2 updated examples

* ESP32S3 updated examples

* ESP32C6 updated examples

* cargo fmt
2023-03-31 09:51:34 +02:00
Björn Quentin
4e88e48bbe
Remove unnecessary rt crate dependencies (#391)
* Remove unnecessary `rt` crate dependencies

* Bump versions, update to latest released dependencies
2023-02-10 07:24:12 -08:00
Jesse Braham
cf270700e7
Use the new esp-riscv-rt package for RISC-V HALs (#365)
* Update PACs and modify `esp-hal-common` to use new `esp-riscv-rt` package

* Update `esp32c2-hal` and `esp32c3-hal` to use `esp-riscv-rt` as well

* Update all RISC-V examples to use `esp-riscv-rt`

* Update RISC-V trap frame handling according to review feedback
2023-01-27 10:49:38 -08:00
Scott Mabin
248fb356f8
PeripheralRef init: uart (#272)
* Add the peripheral module plus some helper macros in preparation

* peripheral macro

* Add peripheral generation macro

* Fixes after rebase

* Update the signature of Peripherals::take

* syncronise hello world example

* fmt the entire repo

Co-authored-by: Jesse Braham <jesse@beta7.io>
2022-12-12 14:45:33 +00:00
Scott Mabin
be184a552d
critical_section implementations & esp_backtrace (#151)
* CS impl

* use CS Mutex in C3 examples

* use CS Mutex in S2 examples

* Update esp32 example

* run fmt

* Update S3 examples

* Remove uses of unsafe where no longer required

* use esp_backtrace in examples

* fix import & fmt once more

* Bump MSRV to 1.60.0

Co-authored-by: Jesse Braham <jesse@beta7.io>
2022-08-22 20:02:28 +01:00
Gustavo Henrique Nihei
91ea205446
ESP32-C3: Add driver for RTC Watchdog Timer (RWDT) (#134)
* esp32: Fix typo in Frequency word in some identifiers

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>

* esp32c3: Add support for PLL clock configuration

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>

* clock: Move definition of Clock types to common level

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>

* esp32c3: Add support for RTC Clock configuration

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>

* esp32c3: Add example for the RTC Watchdog Timer driver

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-08-08 15:36:19 +01:00
Gustavo Henrique Nihei
224e84d9dc
Move Super Watchdog functions into RTC_CNTL common implementation (#125)
* esp32c3: Move SWD functions into RTC_CNTL common implementation

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>

* esp32s3: Extend SWD functions to ESP32-S3

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-27 13:37:37 -07:00
Scott Mabin
1d02bf87c3
RISCV vectored interrupts (#118)
* RISCV interrupt vectoring

- Adds support for vectoring peripheral interrupts to PAC handlers
- Currently supports level interrupts with priorities from 1-15
- Updated the gpio interrupt example to reflect the new changes

* remove .vscode files

* Support vectored edge interrupts

This is as simple as making sure we clear the CPU interrupt whenever we
receive one. This also documents further what APIs are safe to call when
the `vectored` feature is enabled.

* fix all examples to use vectoring

* doc & cleanup

* run handlers from ram

* make xtensa::interrupt::vectored private, we rexport public items

* fix default handlers

* pass interrupt into EspDefaultHandler
2022-07-26 09:24:47 -07:00
Björn Quentin
147d8de988
Separate TIMG into timer0, (timer1), wdt (#104)
* Separate TIMG into timer0, (timer1), wdt
* Apply suggestions from code review
* Remove left-over code
* Ignore settings.json
2022-07-20 06:51:39 -07:00
bjoernQ
35a58490c6 Additional UART/Serial features 2022-07-13 22:46:34 +02:00