esp-hal/xtensa-lx-rt/CHANGELOG.md
Dániel Buga 321ae5ef1b
Rewrite Xtensa startup code in assembly (#4117)
* Initialize rtc RAM in xtensa-lx-rt

* Rewrite CPU reset handler in ASM
2025-09-17 07:57:23 +00:00

1.4 KiB

Changelog

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.

Unreleased

Added

  • A new feature defmt which implements defmt::Format on Context (#3887)

Changed

  • Removed the r0 dependency (#4117)

Fixed

Removed

v0.20.0 - 2025-07-16

Changed

  • MSRV is now 1.88.0 (#3742)

Removed

  • The esp32, esp32s2 and esp32s3 features have been removed. (#3598)

v0.19.0 - 2025-06-03

Changed

  • Bump Rust edition to 2024, bump MSRV to 1.85. (#3391)

0.18.0 - 2025-01-15

Changed

  • Bump MSRV to 1.84 (#2951)

0.17.2 - 2024-11-20

Fixed

  • Fixed saving the state of the FPU co-processor. (#2311)

0.17.1 - 2024-09-02

Added

  • Better diagnostics when using floats inside an interrupt handler when using the default hard fault handler (#2044)

Fixed

  • Store state of FP coprocessor in stack memory (#2057)

Initial releases