Scott Mabin 1d02bf87c3
RISCV vectored interrupts (#118)
* RISCV interrupt vectoring

- Adds support for vectoring peripheral interrupts to PAC handlers
- Currently supports level interrupts with priorities from 1-15
- Updated the gpio interrupt example to reflect the new changes

* remove .vscode files

* Support vectored edge interrupts

This is as simple as making sure we clear the CPU interrupt whenever we
receive one. This also documents further what APIs are safe to call when
the `vectored` feature is enabled.

* fix all examples to use vectoring

* doc & cleanup

* run handlers from ram

* make xtensa::interrupt::vectored private, we rexport public items

* fix default handlers

* pass interrupt into EspDefaultHandler
2022-07-26 09:24:47 -07:00
2021-10-19 15:00:41 -07:00
2021-10-19 15:00:41 -07:00

esp-hal

GitHub Workflow Status MIT/Apache-2.0 licensed Matrix

Hardware Abstraction Layer crates for the ESP32, ESP32-C3, ESP32-S2, and ESP32-S3 from Espressif.

This project is still in the early stages of development, and as such there should be no expectation of API stability. Only a small number of peripherals currently have drivers implemented (you can see a full list here) and out of those most are still incomplete, albeit functional. These HALs are no_std; if you are looking for std support please use esp-idf-hal instead.

If you have any questions, comments, or concerns please join us on Matrix. For additional information regarding any of the crates in the monorepo, please refer to the crate's README.

Crate Target Technical Reference Manual
esp32-hal xtensa-esp32-none-elf ESP32
esp32c3-hal riscv32imc-unknown-none-elf
riscv32imac-unknown-none-elf*
ESP32-C3
esp32s2-hal xtensa-esp32s2-none-elf ESP32-S2
esp32s3-hal xtensa-esp32s3-none-elf ESP32-S3

* via atomic emulation

MSRV

The Minimum Supported Rust Versions are:

  • 1.59.0 for RISC-V devices (ESP32-C3)
  • 1.59.0 for Xtensa devices (ESP32, ESP32-S2, ESP32-S3)

Note that targeting the Xtensa ISA requires the use of the esp-rs/rust compiler fork, whereas RISC-V is officially supported by the official Rust compiler.

License

Licensed under either of:

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Description
no_std Hardware Abstraction Layers for ESP32 microcontrollers
Readme 111 MiB
Languages
Rust 99.8%
Jinja 0.1%