mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-02 14:44:42 +00:00
1d02bf87c3
* RISCV interrupt vectoring - Adds support for vectoring peripheral interrupts to PAC handlers - Currently supports level interrupts with priorities from 1-15 - Updated the gpio interrupt example to reflect the new changes * remove .vscode files * Support vectored edge interrupts This is as simple as making sure we clear the CPU interrupt whenever we receive one. This also documents further what APIs are safe to call when the `vectored` feature is enabled. * fix all examples to use vectoring * doc & cleanup * run handlers from ram * make xtensa::interrupt::vectored private, we rexport public items * fix default handlers * pass interrupt into EspDefaultHandler
esp32c3-hal
no_std HAL for the ESP32-C3 from Espressif. Implements a number of the traits defined by embedded-hal.
This device uses the RISC-V ISA, which is officially supported by the Rust compiler via the riscv32imc-unknown-none-elf target. Refer to the Getting Stared section below for more information.
Documentation
Getting Started
Installing the Rust Compiler Target
The compilation target for this device is officially supported via the stable release channel and can be installed via rustup:
$ rustup target add riscv32imc-unknown-none-elf
License
Licensed under either of:
- Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.