mirror of
https://github.com/esp-rs/esp-hal.git
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8c69e8cb51
* Newtype fugit Rate, Instant and Duration * Document, remove time::now * Fix perf * Tweak docs
789 lines
26 KiB
Rust
789 lines
26 KiB
Rust
//! SPI Full Duplex test suite.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES(unstable): unstable
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//% FEATURES(stable):
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// FIXME: add async test cases that don't rely on PCNT
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#![no_std]
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#![no_main]
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use embedded_hal::spi::SpiBus;
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use embedded_hal_async::spi::SpiBus as SpiBusAsync;
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use esp_hal::{
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spi::master::{Config, Spi},
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time::Rate,
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Blocking,
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};
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use hil_test as _;
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cfg_if::cfg_if! {
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if #[cfg(feature = "unstable")] {
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use esp_hal::{
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dma::{DmaDescriptor, DmaRxBuf, DmaTxBuf},
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dma_buffers,
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gpio::{Level, NoPin},
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};
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#[cfg(pcnt)]
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use esp_hal::{
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gpio::interconnect::InputSignal,
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pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
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};
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}
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}
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#[cfg(feature = "unstable")]
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cfg_if::cfg_if! {
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if #[cfg(any(esp32, esp32s2))] {
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type DmaChannel = esp_hal::dma::Spi2DmaChannel;
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} else {
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type DmaChannel = esp_hal::dma::DmaChannel0;
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}
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}
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struct Context {
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spi: Spi<'static, Blocking>,
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#[cfg(feature = "unstable")]
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dma_channel: DmaChannel,
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// Reuse the really large buffer so we don't run out of DRAM with many tests
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rx_buffer: &'static mut [u8],
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#[cfg(feature = "unstable")]
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rx_descriptors: &'static mut [DmaDescriptor],
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tx_buffer: &'static mut [u8],
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#[cfg(feature = "unstable")]
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tx_descriptors: &'static mut [DmaDescriptor],
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#[cfg(all(pcnt, feature = "unstable"))]
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pcnt_source: InputSignal,
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#[cfg(all(pcnt, feature = "unstable"))]
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pcnt_unit: Unit<'static, 0>,
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}
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#[cfg(test)]
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#[embedded_test::tests(default_timeout = 3, executor = hil_test::Executor::new())]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(
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esp_hal::Config::default().with_cpu_clock(esp_hal::clock::CpuClock::max()),
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);
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let (_, mosi) = hil_test::common_test_pins!(peripherals);
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#[cfg(feature = "unstable")]
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cfg_if::cfg_if! {
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if #[cfg(pdma)] {
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let dma_channel = peripherals.DMA_SPI2;
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} else {
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let dma_channel = peripherals.DMA_CH0;
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}
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}
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cfg_if::cfg_if! {
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if #[cfg(feature = "unstable")] {
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let (miso, mosi) = mosi.split();
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#[cfg(pcnt)]
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let mosi_loopback_pcnt = miso.clone();
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
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} else {
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use esp_hal::peripheral::Peripheral;
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let miso = unsafe { mosi.clone_unchecked() };
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static mut TX_BUFFER: [u8; 4096] = [0; 4096];
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static mut RX_BUFFER: [u8; 4096] = [0; 4096];
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let tx_buffer = unsafe { (&raw mut TX_BUFFER).as_mut().unwrap() };
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let rx_buffer = unsafe { (&raw mut RX_BUFFER).as_mut().unwrap() };
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}
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}
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// Need to set miso first so that mosi can overwrite the
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// output connection (because we are using the same pin to loop back)
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let spi = Spi::new(
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peripherals.SPI2,
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Config::default().with_frequency(Rate::from_mhz(10)),
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)
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.unwrap()
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.with_sck(peripherals.GPIO0)
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.with_miso(miso)
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.with_mosi(mosi);
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cfg_if::cfg_if! {
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if #[cfg(feature = "unstable")] {
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#[cfg(pcnt)]
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let pcnt = Pcnt::new(peripherals.PCNT);
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Context {
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spi,
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rx_buffer,
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tx_buffer,
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dma_channel,
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rx_descriptors,
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tx_descriptors,
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#[cfg(pcnt)]
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pcnt_source: mosi_loopback_pcnt,
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#[cfg(pcnt)]
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pcnt_unit: pcnt.unit0,
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}
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} else {
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Context {
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spi,
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rx_buffer,
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tx_buffer,
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}
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}
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}
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}
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#[test]
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fn test_symmetric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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SpiBus::transfer(&mut ctx.spi, &mut read[..], &write[..])
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.expect("Symmetric transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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async fn test_async_symmetric_transfer(ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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let mut spi = ctx.spi.into_async();
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SpiBusAsync::transfer(&mut spi, &mut read[..], &write[..])
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.await
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.expect("Symmetric transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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fn test_asymmetric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00; 4];
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SpiBus::transfer(&mut ctx.spi, &mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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}
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#[test]
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async fn test_async_asymmetric_transfer(ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00; 4];
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let mut spi = ctx.spi.into_async();
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SpiBusAsync::transfer(&mut spi, &mut read[0..2], &write[..])
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.await
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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}
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#[test]
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#[cfg(all(pcnt, feature = "unstable"))]
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fn test_asymmetric_write(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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SpiBus::write(&mut ctx.spi, &write[..]).expect("Asymmetric write failed");
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// Flush because we're not reading, so the write may happen in the background
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ctx.spi.flush().expect("Flush failed");
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assert_eq!(unit.value(), 9);
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}
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#[test]
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#[cfg(all(pcnt, feature = "unstable"))]
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async fn test_async_asymmetric_write(ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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let mut spi = ctx.spi.into_async();
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SpiBusAsync::write(&mut spi, &write[..])
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.await
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.expect("Asymmetric write failed");
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assert_eq!(unit.value(), 9);
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}
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#[test]
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#[cfg(all(pcnt, feature = "unstable"))]
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async fn async_write_after_sync_write_waits_for_flush(ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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let mut spi = ctx.spi.into_async();
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// Slow down SCLK so that transferring the buffer takes a while.
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spi.apply_config(&Config::default().with_frequency(Rate::from_khz(80)))
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.expect("Apply config failed");
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SpiBus::write(&mut spi, &write[..]).expect("Sync write failed");
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SpiBusAsync::write(&mut spi, &write[..])
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.await
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.expect("Async write failed");
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assert_eq!(unit.value(), 34);
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}
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#[test]
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#[cfg(all(pcnt, feature = "unstable"))]
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fn test_asymmetric_write_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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SpiBus::transfer(&mut ctx.spi, &mut [], &write[..]).expect("Asymmetric transfer failed");
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// Flush because we're not reading, so the write may happen in the background
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ctx.spi.flush().expect("Flush failed");
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assert_eq!(unit.value(), 9);
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}
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#[test]
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#[cfg(all(pcnt, feature = "unstable"))]
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async fn test_async_asymmetric_write_transfer(ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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let mut spi = ctx.spi.into_async();
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SpiBusAsync::transfer(&mut spi, &mut [], &write[..])
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.await
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.expect("Asymmetric transfer failed");
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assert_eq!(unit.value(), 9);
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}
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#[test]
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fn test_symmetric_transfer_huge_buffer(mut ctx: Context) {
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let write = &mut ctx.tx_buffer[0..4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let read = &mut ctx.rx_buffer[0..4096];
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SpiBus::transfer(&mut ctx.spi, &mut read[..], &write[..]).expect("Huge transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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async fn test_async_symmetric_transfer_huge_buffer(ctx: Context) {
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let write = &mut ctx.tx_buffer[0..4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let read = &mut ctx.rx_buffer[0..4096];
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let mut spi = ctx.spi.into_async();
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SpiBusAsync::transfer(&mut spi, &mut read[..], &write[..])
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.await
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.expect("Huge transfer failed");
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for idx in 0..write.len() {
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assert_eq!(write[idx], read[idx], "Mismatch at index {}", idx);
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}
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}
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#[test]
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fn test_symmetric_transfer_huge_buffer_in_place(mut ctx: Context) {
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let write = &mut ctx.tx_buffer[0..4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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ctx.spi
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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}
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#[test]
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async fn test_async_symmetric_transfer_huge_buffer_in_place(ctx: Context) {
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let write = &mut ctx.tx_buffer[0..4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut spi = ctx.spi.into_async();
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SpiBusAsync::transfer_in_place(&mut spi, &mut write[..])
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.await
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.expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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}
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#[test]
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#[cfg(all(pcnt, feature = "unstable"))]
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fn test_dma_read_dma_write_pcnt(ctx: Context) {
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const DMA_BUFFER_SIZE: usize = 8;
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const TRANSFER_SIZE: usize = 5;
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
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let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let unit = ctx.pcnt_unit;
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let mut spi = ctx.spi.with_dma(ctx.dma_channel);
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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dma_rx_buf.set_length(TRANSFER_SIZE);
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dma_tx_buf.set_length(TRANSFER_SIZE);
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// Fill the buffer where each byte has 3 pos edges.
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dma_tx_buf.as_mut_slice().fill(0b0110_1010);
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for i in 1..4 {
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dma_rx_buf.as_mut_slice()[..TRANSFER_SIZE].copy_from_slice(&[5; TRANSFER_SIZE]);
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let transfer = spi
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.read(TRANSFER_SIZE, dma_rx_buf)
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.map_err(|e| e.0)
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.unwrap();
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(spi, dma_rx_buf) = transfer.wait();
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assert_eq!(&dma_rx_buf.as_slice()[..TRANSFER_SIZE], &[0; TRANSFER_SIZE]);
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let transfer = spi
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.write(TRANSFER_SIZE, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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(spi, dma_tx_buf) = transfer.wait();
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assert_eq!(unit.value(), (i * 3 * TRANSFER_SIZE) as _);
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}
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}
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#[test]
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#[cfg(all(pcnt, feature = "unstable"))]
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fn test_dma_read_dma_transfer_pcnt(ctx: Context) {
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const DMA_BUFFER_SIZE: usize = 8;
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const TRANSFER_SIZE: usize = 5;
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
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let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let unit = ctx.pcnt_unit;
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let mut spi = ctx.spi.with_dma(ctx.dma_channel);
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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dma_rx_buf.set_length(TRANSFER_SIZE);
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dma_tx_buf.set_length(TRANSFER_SIZE);
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// Fill the buffer where each byte has 3 pos edges.
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dma_tx_buf.as_mut_slice().fill(0b0110_1010);
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for i in 1..4 {
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dma_rx_buf.as_mut_slice()[..TRANSFER_SIZE].copy_from_slice(&[5; TRANSFER_SIZE]);
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let transfer = spi
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.read(TRANSFER_SIZE, dma_rx_buf)
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.map_err(|e| e.0)
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.unwrap();
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(spi, dma_rx_buf) = transfer.wait();
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assert_eq!(&dma_rx_buf.as_slice()[..TRANSFER_SIZE], &[0; TRANSFER_SIZE]);
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let transfer = spi
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.transfer(TRANSFER_SIZE, dma_rx_buf, TRANSFER_SIZE, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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assert_eq!(unit.value(), (i * 3 * TRANSFER_SIZE) as _);
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}
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}
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#[test]
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#[cfg(feature = "unstable")]
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fn test_symmetric_dma_transfer(ctx: Context) {
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// This test case sends a large amount of data, multiple times to verify that
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// https://github.com/esp-rs/esp-hal/issues/2151 is and remains fixed.
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let mut dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
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for (i, v) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() {
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*v = (i % 255) as u8;
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}
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let mut spi = ctx.spi.with_dma(ctx.dma_channel);
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for i in 0..4 {
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dma_tx_buf.as_mut_slice()[0] = i as u8;
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*dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8;
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let transfer = spi
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.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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if dma_tx_buf.as_slice() != dma_rx_buf.as_slice() {
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defmt::info!("dma_tx_buf: {:?}", dma_tx_buf.as_slice()[0..100]);
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defmt::info!("dma_rx_buf: {:?}", dma_rx_buf.as_slice()[0..100]);
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panic!("Mismatch at iteration {}", i);
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}
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}
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}
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#[test]
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#[cfg(feature = "unstable")]
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fn test_asymmetric_dma_transfer(ctx: Context) {
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const WRITE_SIZE: usize = 4;
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const READ_SIZE: usize = 2;
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4, 4);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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|
|
dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
|
|
|
|
let spi = ctx.spi.with_dma(ctx.dma_channel);
|
|
let transfer = spi
|
|
.transfer(READ_SIZE, dma_rx_buf, WRITE_SIZE, dma_tx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
let (spi, (dma_rx_buf, mut dma_tx_buf)) = transfer.wait();
|
|
assert_eq!(
|
|
dma_tx_buf.as_slice()[0..READ_SIZE],
|
|
dma_rx_buf.as_slice()[0..READ_SIZE]
|
|
);
|
|
|
|
// Try transfer again to make sure DMA isn't in a broken state.
|
|
|
|
dma_tx_buf.fill(&[0xaa, 0xdd, 0xef, 0xbe]);
|
|
|
|
let transfer = spi
|
|
.transfer(READ_SIZE, dma_rx_buf, WRITE_SIZE, dma_tx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
|
|
assert_eq!(
|
|
dma_tx_buf.as_slice()[0..READ_SIZE],
|
|
dma_rx_buf.as_slice()[0..READ_SIZE]
|
|
);
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(all(pcnt, feature = "unstable"))]
|
|
fn test_dma_bus_read_write_pcnt(ctx: Context) {
|
|
const TRANSFER_SIZE: usize = 4;
|
|
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
|
|
let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
|
|
let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
|
|
|
|
ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
|
|
ctx.pcnt_unit
|
|
.channel0
|
|
.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
|
|
|
|
let mut spi = ctx
|
|
.spi
|
|
.with_dma(ctx.dma_channel)
|
|
.with_buffers(dma_rx_buf, dma_tx_buf);
|
|
|
|
// Fill the buffer where each byte has 3 pos edges.
|
|
let tx_buf = [0b0110_1010; TRANSFER_SIZE];
|
|
let mut rx_buf = [0; TRANSFER_SIZE];
|
|
|
|
for i in 1..4 {
|
|
// Preset as 5, expect 0 repeated receive
|
|
rx_buf.copy_from_slice(&[5; TRANSFER_SIZE]);
|
|
spi.read(&mut rx_buf).unwrap();
|
|
assert_eq!(rx_buf, [0; TRANSFER_SIZE]);
|
|
|
|
spi.write(&tx_buf).unwrap();
|
|
assert_eq!(ctx.pcnt_unit.value(), (i * 3 * TRANSFER_SIZE) as _);
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(feature = "unstable")]
|
|
fn test_dma_bus_symmetric_transfer(ctx: Context) {
|
|
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
|
|
let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
|
|
let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
|
|
|
|
let mut spi = ctx
|
|
.spi
|
|
.with_dma(ctx.dma_channel)
|
|
.with_buffers(dma_rx_buf, dma_tx_buf);
|
|
|
|
let tx_buf = [0xde, 0xad, 0xbe, 0xef];
|
|
let mut rx_buf = [0; 4];
|
|
|
|
spi.transfer(&mut rx_buf, &tx_buf).unwrap();
|
|
|
|
assert_eq!(tx_buf, rx_buf);
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(feature = "unstable")]
|
|
fn test_dma_bus_asymmetric_transfer(ctx: Context) {
|
|
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
|
|
let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
|
|
let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
|
|
|
|
let mut spi = ctx
|
|
.spi
|
|
.with_dma(ctx.dma_channel)
|
|
.with_buffers(dma_rx_buf, dma_tx_buf);
|
|
|
|
let tx_buf = [0xde, 0xad, 0xbe, 0xef];
|
|
let mut rx_buf = [0; 4];
|
|
|
|
spi.transfer(&mut rx_buf, &tx_buf).unwrap();
|
|
|
|
assert_eq!(&tx_buf[0..1], &rx_buf[0..1]);
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(feature = "unstable")]
|
|
fn test_dma_bus_symmetric_transfer_huge_buffer(ctx: Context) {
|
|
const DMA_BUFFER_SIZE: usize = 4096;
|
|
|
|
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(40);
|
|
let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
|
|
let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
|
|
|
|
let mut spi = ctx
|
|
.spi
|
|
.with_dma(ctx.dma_channel)
|
|
.with_buffers(dma_rx_buf, dma_tx_buf);
|
|
|
|
let tx_buf = core::array::from_fn(|i| i as _);
|
|
let mut rx_buf = [0; DMA_BUFFER_SIZE];
|
|
|
|
spi.transfer(&mut rx_buf, &tx_buf).unwrap();
|
|
|
|
assert_eq!(tx_buf, rx_buf);
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(all(pcnt, feature = "unstable"))]
|
|
async fn test_async_dma_read_dma_write_pcnt(ctx: Context) {
|
|
const DMA_BUFFER_SIZE: usize = 8;
|
|
const TRANSFER_SIZE: usize = 5;
|
|
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
|
|
let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
|
|
let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
|
|
let mut spi = ctx
|
|
.spi
|
|
.with_dma(ctx.dma_channel)
|
|
.with_buffers(dma_rx_buf, dma_tx_buf)
|
|
.into_async();
|
|
|
|
ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
|
|
ctx.pcnt_unit
|
|
.channel0
|
|
.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
|
|
|
|
let mut receive = [0; TRANSFER_SIZE];
|
|
|
|
// Fill the buffer where each byte has 3 pos edges.
|
|
let transmit = [0b0110_1010; TRANSFER_SIZE];
|
|
|
|
for i in 1..4 {
|
|
receive.copy_from_slice(&[5; TRANSFER_SIZE]);
|
|
SpiBusAsync::read(&mut spi, &mut receive).await.unwrap();
|
|
assert_eq!(receive, [0; TRANSFER_SIZE]);
|
|
|
|
SpiBusAsync::write(&mut spi, &transmit).await.unwrap();
|
|
assert_eq!(ctx.pcnt_unit.value(), (i * 3 * TRANSFER_SIZE) as _);
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(all(pcnt, feature = "unstable"))]
|
|
async fn test_async_dma_read_dma_transfer_pcnt(ctx: Context) {
|
|
const DMA_BUFFER_SIZE: usize = 8;
|
|
const TRANSFER_SIZE: usize = 5;
|
|
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
|
|
let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
|
|
let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
|
|
let mut spi = ctx
|
|
.spi
|
|
.with_dma(ctx.dma_channel)
|
|
.with_buffers(dma_rx_buf, dma_tx_buf)
|
|
.into_async();
|
|
|
|
ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
|
|
ctx.pcnt_unit
|
|
.channel0
|
|
.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
|
|
|
|
let mut receive = [0; TRANSFER_SIZE];
|
|
|
|
// Fill the buffer where each byte has 3 pos edges.
|
|
let transmit = [0b0110_1010; TRANSFER_SIZE];
|
|
|
|
for i in 1..4 {
|
|
receive.copy_from_slice(&[5, 5, 5, 5, 5]);
|
|
SpiBusAsync::read(&mut spi, &mut receive).await.unwrap();
|
|
assert_eq!(receive, [0, 0, 0, 0, 0]);
|
|
|
|
SpiBusAsync::transfer(&mut spi, &mut receive, &transmit)
|
|
.await
|
|
.unwrap();
|
|
assert_eq!(ctx.pcnt_unit.value(), (i * 3 * TRANSFER_SIZE) as _);
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(feature = "unstable")]
|
|
fn test_write_read(ctx: Context) {
|
|
let spi = ctx
|
|
.spi
|
|
.with_mosi(NoPin)
|
|
.with_miso(Level::High)
|
|
.with_dma(ctx.dma_channel);
|
|
|
|
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
|
|
let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
|
|
let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
|
|
|
|
dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
|
|
|
|
let transfer = spi
|
|
.write(dma_tx_buf.len(), dma_tx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
let (spi, dma_tx_buf) = transfer.wait();
|
|
|
|
dma_rx_buf.as_mut_slice().fill(0);
|
|
let transfer = spi
|
|
.read(dma_rx_buf.len(), dma_rx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
let (spi, mut dma_rx_buf) = transfer.wait();
|
|
|
|
let transfer = spi
|
|
.write(dma_tx_buf.len(), dma_tx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
let (spi, _dma_tx_buf) = transfer.wait();
|
|
|
|
dma_rx_buf.as_mut_slice().fill(0);
|
|
let transfer = spi
|
|
.read(dma_rx_buf.len(), dma_rx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
let (_, dma_rx_buf) = transfer.wait();
|
|
|
|
assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(feature = "unstable")]
|
|
fn cancel_stops_transaction(mut ctx: Context) {
|
|
// Slow down. At 80kHz, the transfer is supposed to take a bit over 3 seconds.
|
|
// This means that without working cancellation, the test case should
|
|
// fail.
|
|
ctx.spi
|
|
.apply_config(&Config::default().with_frequency(Rate::from_khz(80)))
|
|
.unwrap();
|
|
|
|
// Set up a large buffer that would trigger a timeout
|
|
let dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
|
|
let dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
|
|
|
|
let spi = ctx.spi.with_dma(ctx.dma_channel);
|
|
|
|
let mut transfer = spi
|
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
|
|
transfer.cancel();
|
|
transfer.wait();
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(feature = "unstable")]
|
|
fn can_transmit_after_cancel(mut ctx: Context) {
|
|
// Slow down. At 80kHz, the transfer is supposed to take a bit over 3 seconds.
|
|
ctx.spi
|
|
.apply_config(&Config::default().with_frequency(Rate::from_khz(80)))
|
|
.unwrap();
|
|
|
|
// Set up a large buffer that would trigger a timeout
|
|
let mut dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
|
|
let mut dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
|
|
|
|
let mut spi = ctx.spi.with_dma(ctx.dma_channel);
|
|
|
|
let mut transfer = spi
|
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
|
|
transfer.cancel();
|
|
(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
|
|
|
|
spi.apply_config(&Config::default().with_frequency(Rate::from_mhz(10)))
|
|
.unwrap();
|
|
|
|
let transfer = spi
|
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
|
|
let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
|
|
if dma_tx_buf.as_slice() != dma_rx_buf.as_slice() {
|
|
defmt::info!("dma_tx_buf: {:?}", dma_tx_buf.as_slice()[0..100]);
|
|
defmt::info!("dma_rx_buf: {:?}", dma_rx_buf.as_slice()[0..100]);
|
|
panic!("Failed to transmit after cancel");
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
#[cfg(feature = "unstable")]
|
|
async fn cancelling_an_awaited_transfer_does_nothing(ctx: Context) {
|
|
// Set up a large buffer that would trigger a timeout
|
|
let dma_rx_buf = DmaRxBuf::new(ctx.rx_descriptors, ctx.rx_buffer).unwrap();
|
|
let dma_tx_buf = DmaTxBuf::new(ctx.tx_descriptors, ctx.tx_buffer).unwrap();
|
|
|
|
let spi = ctx.spi.with_dma(ctx.dma_channel).into_async();
|
|
|
|
let mut transfer = spi
|
|
.transfer(dma_rx_buf.len(), dma_rx_buf, dma_tx_buf.len(), dma_tx_buf)
|
|
.map_err(|e| e.0)
|
|
.unwrap();
|
|
|
|
transfer.wait_for_done().await;
|
|
transfer.cancel();
|
|
|
|
transfer.wait_for_done().await;
|
|
transfer.cancel();
|
|
_ = transfer.wait();
|
|
}
|
|
}
|