mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-02 14:44:42 +00:00
163 lines
4.6 KiB
Rust
163 lines
4.6 KiB
Rust
#![no_std]
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#![no_main]
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use core::{cell::RefCell, fmt::Write};
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use bare_metal::Mutex;
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use esp32c3_hal::{
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interrupt,
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pac::{self, Peripherals, UART0},
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prelude::*,
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systimer::{Alarm, SystemTimer, Target},
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Cpu,
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RtcCntl,
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Serial,
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Timer,
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};
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use panic_halt as _;
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use riscv_rt::entry;
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static mut SERIAL: Mutex<RefCell<Option<Serial<UART0>>>> = Mutex::new(RefCell::new(None));
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static mut ALARM0: Mutex<RefCell<Option<Alarm<Target, 0>>>> = Mutex::new(RefCell::new(None));
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static mut ALARM1: Mutex<RefCell<Option<Alarm<Target, 1>>>> = Mutex::new(RefCell::new(None));
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static mut ALARM2: Mutex<RefCell<Option<Alarm<Target, 2>>>> = Mutex::new(RefCell::new(None));
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
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// the RTC WDT, and the TIMG WDTs.
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let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
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let mut timer0 = Timer::new(peripherals.TIMG0);
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let mut timer1 = Timer::new(peripherals.TIMG1);
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let mut serial0 = Serial::new(peripherals.UART0).unwrap();
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rtc_cntl.set_super_wdt_enable(false);
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rtc_cntl.set_wdt_enable(false);
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timer0.disable();
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timer1.disable();
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writeln!(serial0, "SYSTIMER Demo start!").ok();
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let syst = SystemTimer::new(peripherals.SYSTIMER);
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writeln!(serial0, "SYSTIMER Current value = {}", SystemTimer::now()).ok();
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let alarm0 = syst.alarm0;
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alarm0.set_target(40_000_000);
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alarm0.enable_interrupt();
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let alarm1 = syst.alarm1;
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alarm1.set_target(41_111_111);
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alarm1.enable_interrupt();
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let alarm2 = syst.alarm2;
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alarm2.set_target(42_222_222 * 2);
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alarm2.enable_interrupt();
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interrupt::enable(
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Cpu::ProCpu,
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pac::Interrupt::SYSTIMER_TARGET0,
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interrupt::CpuInterrupt::Interrupt1,
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);
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interrupt::enable(
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Cpu::ProCpu,
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pac::Interrupt::SYSTIMER_TARGET1,
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interrupt::CpuInterrupt::Interrupt2,
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);
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interrupt::enable(
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Cpu::ProCpu,
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pac::Interrupt::SYSTIMER_TARGET2,
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interrupt::CpuInterrupt::Interrupt3,
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);
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interrupt::set_kind(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt1,
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interrupt::InterruptKind::Level,
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);
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interrupt::set_kind(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt2,
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interrupt::InterruptKind::Level,
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);
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interrupt::set_kind(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt3,
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interrupt::InterruptKind::Level,
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);
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interrupt::set_priority(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt1,
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interrupt::Priority::Priority1,
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);
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interrupt::set_priority(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt2,
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interrupt::Priority::Priority1,
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);
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interrupt::set_priority(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt3,
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interrupt::Priority::Priority1,
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);
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riscv::interrupt::free(|_cs| unsafe {
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SERIAL.get_mut().replace(Some(serial0));
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ALARM0.get_mut().replace(Some(alarm0));
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ALARM1.get_mut().replace(Some(alarm1));
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ALARM2.get_mut().replace(Some(alarm2));
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});
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unsafe {
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riscv::interrupt::enable();
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}
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loop {}
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}
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#[no_mangle]
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pub fn interrupt1() {
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riscv::interrupt::free(|cs| unsafe {
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let mut serial = SERIAL.borrow(*cs).borrow_mut();
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let serial = serial.as_mut().unwrap();
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writeln!(serial, "Interrupt 1 = {}", SystemTimer::now()).ok();
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let mut alarm = ALARM0.borrow(*cs).borrow_mut();
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let alarm = alarm.as_mut().unwrap();
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interrupt::clear(Cpu::ProCpu, interrupt::CpuInterrupt::Interrupt1);
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alarm.clear_interrupt();
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});
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}
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#[no_mangle]
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pub fn interrupt2() {
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riscv::interrupt::free(|cs| unsafe {
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let mut serial = SERIAL.borrow(*cs).borrow_mut();
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let serial = serial.as_mut().unwrap();
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writeln!(serial, "Interrupt 2 = {}", SystemTimer::now()).ok();
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let mut alarm = ALARM1.borrow(*cs).borrow_mut();
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let alarm = alarm.as_mut().unwrap();
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interrupt::clear(Cpu::ProCpu, interrupt::CpuInterrupt::Interrupt2);
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alarm.clear_interrupt();
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});
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}
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#[no_mangle]
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pub fn interrupt3() {
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riscv::interrupt::free(|cs| unsafe {
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let mut serial = SERIAL.borrow(*cs).borrow_mut();
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let serial = serial.as_mut().unwrap();
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writeln!(serial, "Interrupt 3 = {}", SystemTimer::now()).ok();
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let mut alarm = ALARM2.borrow(*cs).borrow_mut();
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let alarm = alarm.as_mut().unwrap();
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interrupt::clear(Cpu::ProCpu, interrupt::CpuInterrupt::Interrupt3);
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alarm.clear_interrupt();
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});
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}
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