mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-29 21:30:39 +00:00
123 lines
3.2 KiB
Rust
123 lines
3.2 KiB
Rust
#![no_std]
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#![no_main]
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use core::{cell::RefCell, fmt::Write};
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use bare_metal::Mutex;
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use esp32c3_hal::{
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interrupt,
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pac::{self, Peripherals, TIMG0, TIMG1, UART0},
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prelude::*,
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Cpu,
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RtcCntl,
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Serial,
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Timer,
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};
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use panic_halt as _;
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use riscv_rt::entry;
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static mut SERIAL: Mutex<RefCell<Option<Serial<UART0>>>> = Mutex::new(RefCell::new(None));
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static mut TIMER0: Mutex<RefCell<Option<Timer<TIMG0>>>> = Mutex::new(RefCell::new(None));
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static mut TIMER1: Mutex<RefCell<Option<Timer<TIMG1>>>> = Mutex::new(RefCell::new(None));
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
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// the RTC WDT, and the TIMG WDTs.
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let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
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let mut timer0 = Timer::new(peripherals.TIMG0);
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let mut timer1 = Timer::new(peripherals.TIMG1);
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let serial0 = Serial::new(peripherals.UART0).unwrap();
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rtc_cntl.set_super_wdt_enable(false);
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rtc_cntl.set_wdt_enable(false);
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timer0.disable();
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timer1.disable();
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interrupt::enable(
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Cpu::ProCpu,
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pac::Interrupt::TG0_T0_LEVEL,
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interrupt::CpuInterrupt::Interrupt1,
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);
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interrupt::set_kind(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt1,
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interrupt::InterruptKind::Level,
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);
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interrupt::set_priority(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt1,
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interrupt::Priority::Priority1,
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);
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timer0.start(10_000_000u64);
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timer0.listen();
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interrupt::enable(
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Cpu::ProCpu,
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pac::Interrupt::TG1_T0_LEVEL,
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interrupt::CpuInterrupt::Interrupt11,
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);
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interrupt::set_kind(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt11,
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interrupt::InterruptKind::Level,
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);
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interrupt::set_priority(
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Cpu::ProCpu,
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interrupt::CpuInterrupt::Interrupt11,
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interrupt::Priority::Priority1,
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);
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timer1.start(20_000_000u64);
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timer1.listen();
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riscv::interrupt::free(|_cs| unsafe {
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SERIAL.get_mut().replace(Some(serial0));
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TIMER0.get_mut().replace(Some(timer0));
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TIMER1.get_mut().replace(Some(timer1));
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});
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unsafe {
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riscv::interrupt::enable();
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}
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loop {}
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}
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#[no_mangle]
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pub fn interrupt1() {
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riscv::interrupt::free(|cs| unsafe {
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let mut serial = SERIAL.borrow(*cs).borrow_mut();
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let serial = serial.as_mut().unwrap();
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writeln!(serial, "Interrupt 1").ok();
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let mut timer0 = TIMER0.borrow(*cs).borrow_mut();
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let timer0 = timer0.as_mut().unwrap();
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interrupt::clear(Cpu::ProCpu, interrupt::CpuInterrupt::Interrupt1);
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timer0.clear_interrupt();
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timer0.start(10_000_000u64);
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});
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}
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#[no_mangle]
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pub fn interrupt11() {
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riscv::interrupt::free(|cs| unsafe {
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let mut serial = SERIAL.borrow(*cs).borrow_mut();
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let serial = serial.as_mut().unwrap();
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writeln!(serial, "Interrupt 11").ok();
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let mut timer1 = TIMER1.borrow(*cs).borrow_mut();
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let timer1 = timer1.as_mut().unwrap();
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interrupt::clear(Cpu::ProCpu, interrupt::CpuInterrupt::Interrupt11);
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timer1.clear_interrupt();
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timer1.start(20_000_000u64);
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});
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}
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