Scott Mabin ec8308058b

Riscv stable CI (#1491) ...

* Remove interrupt and thread executor embassy features

* Reserve sw interrupt 3 (4) instead of 0 for multicore systems with the embassy feature enabled

* Add thread mode context id and fix up examples

* Use stable rust for riscv CI

* Add binary-logs feature to 8021504 driver

* Add binary-logs feature to 8021504 driver

2024-05-22 16:36:39 +00:00

..

bin

Riscv stable CI (#1491)

2024-05-22 16:36:39 +00:00

lib.rs

[1/3] Timer abstraction: refactor systimer and timer modules into a common timer module (#1527)

2024-05-02 13:27:33 +00:00