mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-29 21:30:39 +00:00
2fe27536aa
* common/spi: Turn fifo size into const instead of hard-coding it into the code in various places. * common/spi: Alias `write_bytes` to `send_bytes` since they share the same interface and the same code anyway. * common/spi: Implement `read_bytes` as counterpart to `send_bytes` that is responsible only for reading bytes received via SPI. * common/spi: Rewrite `transfer` to use `send_bytes` and `read_bytes` under the hood and remove duplicate code. * common/spi: Create submodule for embedded_hal_1 that is re-exported when the `eh1` feature flag is active. This removes lots of duplicate `#[cfg(...)]` macros previously part of the code. * common/spi: Implement `SpiBus` and `SpiBusWrite` traits from the `embedded-hal 1.0.0-alpha.8`. * common/spi: Make `mosi` pin optional * esp32-hal: Add new SPI example with `eh1` traits * esp32-hal/examples/spi_eh1: Add huge transfer and bump the SPI speed to 1 MHz. * common/spi: Apply rustfmt * common/spi: Use `memcpy` to read from registers This cuts down the time between consecutive transfers from about 2 ms to less than 1 ms. * WIP: common/spi: Use `ptr::copy` to fill write FIFO cutting down the time between transfers from just below 1 ms to ~370 us. The implementation is currently broken in that it will always fill the entire FIFO from the input it is given, even if that isn't FIFO-sized... * common/spi: Add more documentation * esp32/examples/spi_eh1: Fix `transfer_in_place` * esp32/examples/spi_eh1: Add conditional compile and compile a dummy instead when the "eh1" feature isn't present. * esp32-hal: Ignore spi_eh1 example in normal builds, where the feature flag "eh1" isn't given. Building the example directly via `cargo build --example spi_eh1_loopback` will now print an error that this requires a feature flag to be active. * common/spi: Use `write_bytes` and drop `send_bytes` instead. Previoulsy, both served the same purpose, but `send_bytes` was introduced more recently and is hence less likely to cause breaking changes in existing code. * common/spi: Fix mosi pin setup * Add SPI examples with ehal 1.0.0-alpha8 traits to all targets. * common/spi: Fix `read` behavior The previous `read` implementation would only read the contents of the SPI receive FIFO and return that as data. However, the `SpiBusRead` trait defines that while reading, bytes should be written out to the bus (Because SPI is transactional, without writing nothing can be read). Reimplements the `embedded-hal` traits to correctly implement this behavior. * common/spi: Use full FIFO size on all variants All esp variants except for the esp32s2 have a 64 byte FIFO, whereas the esp32s2 has a 72 byte FIFO. * common/spi: Use common pad byte for empty writes * common/spi: Fix reading bytes from FIFO by reverting to the old method of reading 32 bytes at a time and assembling the return buffer from that. It turns out that the previous `core::slice::from_raw_parts()` doesn't work for the esp32s2 and esp32s3 variants, returning bogus data even though the correct data is present in the registers. * common/spi: Fix typos * examples: Fix spi_eh1_loopback examples