mirror of
https://github.com/esp-rs/esp-hal.git
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ff2a46dbc8
* Make async operations cancellable * Handle thresholds * Fix written amount calculation * Fix waiting for events * Don't return 0 bytes, don't modify TX threshold * Add read_exact implementation * Fix tests * Add tests * Inline constant into the default values * Make FIFO config stable * Fix doc links * Changelog * Remove duplicate changelog entries * Check for RX error * Fix write_async not recalculating available space * Fix ESP32 timeout loop * Check the unmasked interrupt bits to actually detect errors * Improve naming * Change async handler to not clear interrupt status * Test and fix case where write_async returned Ok(0) * Tweak docs * Address review feedback * Use embedded_io to fill buffer in test * Rename
47 lines
1.2 KiB
Rust
47 lines
1.2 KiB
Rust
//! Misc UART TX/RX regression tests
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: unstable
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#![no_std]
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#![no_main]
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#[cfg(test)]
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#[embedded_test::tests(default_timeout = 3)]
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mod tests {
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use esp_hal::{
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gpio::Flex,
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uart::{self, UartRx, UartTx},
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};
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use hil_test as _;
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#[test]
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fn test_that_creating_tx_does_not_cause_a_pulse() {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let (rx, tx) = hil_test::common_test_pins!(peripherals);
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let mut rx = UartRx::new(peripherals.UART1, uart::Config::default())
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.unwrap()
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.with_rx(rx);
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// Start from a low level to verify that UartTx sets the level high initially,
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// but don't enable output otherwise we actually pull down against RX's
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// pullup resistor.
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let mut tx = Flex::new(tx);
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tx.set_low();
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// set up TX and send a byte
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let mut tx = UartTx::new(peripherals.UART0, uart::Config::default())
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.unwrap()
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.with_tx(tx);
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tx.flush().unwrap();
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tx.write(&[0x42]).unwrap();
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let mut byte = [0u8; 1];
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rx.read(&mut byte).unwrap();
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assert_eq!(byte[0], 0x42);
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}
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}
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