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Get rid of the riscv-ulp-hal feature

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This commit is contained in:
ivmarkov 2024-01-18 20:12:27 +00:00
parent eefb213469
commit e79df5a873
19 changed files with 144 additions and 1694 deletions
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9
.github/workflows/ci.yml vendored
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@ -65,24 +65,19 @@ jobs:
RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}" RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}"
run: cargo build --target ${{ matrix.target }} --features nightly,critical-section,embassy-sync -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort run: cargo build --target ${{ matrix.target }} --features nightly,critical-section,embassy-sync -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort
- name: Build | RISCV-ULP-HAL feature
env:
ESP_IDF_VERSION: ${{ matrix.idf-version }}
run: cargo build --features riscv-ulp-hal --no-default-features --target riscv32imc-unknown-none-elf -Zbuild-std=core,panic_abort -Zbuild-std-features=panic_immediate_abort
- name: Build | Compile, no_std - name: Build | Compile, no_std
env: env:
ESP_IDF_VERSION: ${{ matrix.idf-version }} ESP_IDF_VERSION: ${{ matrix.idf-version }}
ESP_IDF_SDKCONFIG_DEFAULTS: "${{ github.workspace }}/.github/configs/sdkconfig.defaults" ESP_IDF_SDKCONFIG_DEFAULTS: "${{ github.workspace }}/.github/configs/sdkconfig.defaults"
RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}" RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}"
run: cargo build --features esp-idf-sys --no-default-features --target ${{ matrix.target }} -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort run: cargo build --no-default-features --target ${{ matrix.target }} -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort
- name: Build | Compile, no_std, alloc - name: Build | Compile, no_std, alloc
env: env:
ESP_IDF_VERSION: ${{ matrix.idf-version }} ESP_IDF_VERSION: ${{ matrix.idf-version }}
ESP_IDF_SDKCONFIG_DEFAULTS: "${{ github.workspace }}/.github/configs/sdkconfig.defaults" ESP_IDF_SDKCONFIG_DEFAULTS: "${{ github.workspace }}/.github/configs/sdkconfig.defaults"
RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}" RUSTFLAGS: "${{ matrix.idf-version == 'release/v5.1' && '--cfg espidf_time64' || ''}}"
run: cargo build --features alloc,esp-idf-sys --no-default-features --target ${{ matrix.target }} -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort run: cargo build --features alloc --no-default-features --target ${{ matrix.target }} -Zbuild-std=std,panic_abort -Zbuild-std-features=panic_immediate_abort
- name: Setup | ldproxy - name: Setup | ldproxy
if: matrix.target == 'riscv32imc-esp-espidf' if: matrix.target == 'riscv32imc-esp-espidf'

1
CHANGELOG.md
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@ -6,6 +6,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
## [?.??.?] - ????-??-?? ## [?.??.?] - ????-??-??
* Breaking change: feature `riscv-ulp-hal` (and consequently, feature `esp-idf-sys`) is now removed. Use the [esp-ulp-riscv-hal](https://github.com/esp-rs/esp-hal/tree/main/esp-ulp-riscv-hal) crate instead
* MSRV 1.75; remove the nightly feature flag from all async trait implementations * MSRV 1.75; remove the nightly feature flag from all async trait implementations
* Update public dependencies `e-hal` to 1.0.0 and `embassy-sync` to 0.5 and private dependency `heapless` to 0.8 * Update public dependencies `e-hal` to 1.0.0 and `embassy-sync` to 0.5 and private dependency `heapless` to 0.8
* Allow `cargo check --all-features` to work correctly (there used to be a build error when both the `esp-idf-sys` and the `riscv-ulp-hal` features were enabled) * Allow `cargo check --all-features` to work correctly (there used to be a build error when both the `esp-idf-sys` and the `riscv-ulp-hal` features were enabled)

6
Cargo.toml
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@ -23,8 +23,6 @@ default = ["std", "binstart"]
std = ["alloc", "esp-idf-sys/std"] std = ["alloc", "esp-idf-sys/std"]
alloc = [] alloc = []
nightly = [] nightly = []
esp-idf-sys = ["dep:esp-idf-sys", "atomic-waker"]
riscv-ulp-hal = []
wake-from-isr = [] # Only enable if you plan to use the `edge-executor` crate wake-from-isr = [] # Only enable if you plan to use the `edge-executor` crate
embassy-sync = [] # For now, the dependecy on the `embassy-sync` crate is non-optional, but this might change in future embassy-sync = [] # For now, the dependecy on the `embassy-sync` crate is non-optional, but this might change in future
@ -45,13 +43,13 @@ embedded-hal-nb = "1"
embedded-hal-async = "1" embedded-hal-async = "1"
embedded-io = "0.6" embedded-io = "0.6"
embedded-io-async = "0.6" embedded-io-async = "0.6"
esp-idf-sys = { version = "0.33.7", optional = true, default-features = false } esp-idf-sys = { version = "0.33.7", default-features = false }
critical-section = { version = "1.1.1", optional = true } critical-section = { version = "1.1.1", optional = true }
heapless = "0.8" heapless = "0.8"
num_enum = { version = "0.7", default-features = false } num_enum = { version = "0.7", default-features = false }
enumset = { version = "1", default-features = false } enumset = { version = "1", default-features = false }
log = { version = "0.4", default-features = false } log = { version = "0.4", default-features = false }
atomic-waker = { version = "1.1.1", optional = true, default-features = false } atomic-waker = { version = "1.1.1", default-features = false }
embassy-sync = { version = "0.5" } embassy-sync = { version = "0.5" }
[build-dependencies] [build-dependencies]

22
build.rs
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@ -1,26 +1,4 @@
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
fn main() { fn main() {
embuild::espidf::sysenv::relay(); embuild::espidf::sysenv::relay();
embuild::espidf::sysenv::output(); // Only necessary for building the examples embuild::espidf::sysenv::output(); // Only necessary for building the examples
} }
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
fn main() {
println!("cargo:rustc-cfg=esp32s2");
let riscv_ulp_dir = std::env::current_dir().unwrap().join("riscv-ulp");
println!("cargo:rustc-link-search={}", riscv_ulp_dir.display());
println!(
"cargo:rerun-if-changed={}",
riscv_ulp_dir.join("libriscv_ulp_start.a").display()
);
println!(
"cargo:rerun-if-changed={}",
riscv_ulp_dir.join("riscv_ulp_link_base.x").display()
);
println!(
"cargo:rerun-if-changed={}",
riscv_ulp_dir.join("riscv_ulp_link_default.x").display()
);
}

15
examples/pcnt_rotary_encoder.rs
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@ -6,10 +6,7 @@
//! threshold and track how much that accounts for and provide an i32 value result //! threshold and track how much that accounts for and provide an i32 value result
//! //!
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
fn main() -> anyhow::Result<()> { fn main() -> anyhow::Result<()> {
use anyhow::Context; use anyhow::Context;
use encoder::Encoder; use encoder::Encoder;
@ -38,10 +35,7 @@ fn main() -> anyhow::Result<()> {
} }
} }
#[cfg(not(all( #[cfg(not(any(esp32, esp32s2, esp32s3)))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
)))]
fn main() { fn main() {
use esp_idf_hal::delay::FreeRtos; use esp_idf_hal::delay::FreeRtos;
println!("pcnt peripheral not supported on this device!"); println!("pcnt peripheral not supported on this device!");
@ -50,10 +44,7 @@ fn main() {
} }
} }
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
// esp-idf encoder implementation using v4 pcnt api // esp-idf encoder implementation using v4 pcnt api
mod encoder { mod encoder {
use std::cmp::min; use std::cmp::min;

31
src/adc.rs
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@ -1,20 +1,12 @@
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use esp_idf_sys::*; use esp_idf_sys::*;
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
use crate::riscv_ulp_hal::sys::*;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::gpio::ADCPin; use crate::gpio::ADCPin;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::peripheral::{Peripheral, PeripheralRef}; use crate::peripheral::{Peripheral, PeripheralRef};
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub type AdcConfig = config::Config; pub type AdcConfig = config::Config;
#[cfg(all( #[cfg(all(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(esp_idf_version_major = "4"), not(esp_idf_version_major = "4"),
not(esp32c2), not(esp32c2),
esp_idf_comp_esp_adc_enabled esp_idf_comp_esp_adc_enabled
@ -30,7 +22,6 @@ pub trait Adc: Send {
} }
// NOTE: Will be changed to an enum once C-style enums are usable as const generics // NOTE: Will be changed to an enum once C-style enums are usable as const generics
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod attenuation { pub mod attenuation {
pub use esp_idf_sys::{ pub use esp_idf_sys::{
adc_atten_t, adc_atten_t_ADC_ATTEN_DB_0, adc_atten_t_ADC_ATTEN_DB_11, adc_atten_t, adc_atten_t_ADC_ATTEN_DB_0, adc_atten_t_ADC_ATTEN_DB_11,
@ -44,7 +35,6 @@ pub mod attenuation {
} }
/// ADC configuration /// ADC configuration
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod config { pub mod config {
use esp_idf_sys::*; use esp_idf_sys::*;
@ -119,12 +109,10 @@ pub mod config {
} }
} }
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub struct AdcChannelDriver<'d, const A: adc_atten_t, T: ADCPin> { pub struct AdcChannelDriver<'d, const A: adc_atten_t, T: ADCPin> {
pin: PeripheralRef<'d, T>, pin: PeripheralRef<'d, T>,
} }
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
impl<'d, const A: adc_atten_t, T: ADCPin> AdcChannelDriver<'d, A, T> { impl<'d, const A: adc_atten_t, T: ADCPin> AdcChannelDriver<'d, A, T> {
pub fn new(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> { pub fn new(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin); crate::into_ref!(pin);
@ -151,7 +139,6 @@ impl<'d, const A: adc_atten_t, T: ADCPin> AdcChannelDriver<'d, A, T> {
} }
} }
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
impl<'d, const A: adc_atten_t, T: ADCPin> embedded_hal_0_2::adc::Channel<T::Adc> impl<'d, const A: adc_atten_t, T: ADCPin> embedded_hal_0_2::adc::Channel<T::Adc>
for AdcChannelDriver<'d, A, T> for AdcChannelDriver<'d, A, T>
{ {
@ -162,7 +149,6 @@ impl<'d, const A: adc_atten_t, T: ADCPin> embedded_hal_0_2::adc::Channel<T::Adc>
} }
} }
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub struct AdcDriver<'d, ADC: Adc> { pub struct AdcDriver<'d, ADC: Adc> {
_adc: PeripheralRef<'d, ADC>, _adc: PeripheralRef<'d, ADC>,
#[allow(dead_code)] #[allow(dead_code)]
@ -175,10 +161,8 @@ pub struct AdcDriver<'d, ADC: Adc> {
Option<[Option<esp_adc_cal_characteristics_t>; adc_atten_t_ADC_ATTEN_DB_11 as usize + 1]>, Option<[Option<esp_adc_cal_characteristics_t>; adc_atten_t_ADC_ATTEN_DB_11 as usize + 1]>,
} }
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
unsafe impl<'d, ADC: Adc> Send for AdcDriver<'d, ADC> {} unsafe impl<'d, ADC: Adc> Send for AdcDriver<'d, ADC> {}
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
impl<'d, ADC: Adc> AdcDriver<'d, ADC> { impl<'d, ADC: Adc> AdcDriver<'d, ADC> {
#[cfg(all( #[cfg(all(
esp32, esp32,
@ -403,7 +387,6 @@ impl<'d, ADC: Adc> AdcDriver<'d, ADC> {
} }
} }
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
impl<'d, 'c, const A: adc_atten_t, T> impl<'d, 'c, const A: adc_atten_t, T>
embedded_hal_0_2::adc::OneShot<T::Adc, u16, AdcChannelDriver<'c, A, T>> embedded_hal_0_2::adc::OneShot<T::Adc, u16, AdcChannelDriver<'c, A, T>>
for AdcDriver<'d, T::Adc> for AdcDriver<'d, T::Adc>
@ -418,11 +401,7 @@ where
} }
} }
#[cfg(all( #[cfg(all(esp32, esp_idf_version_major = "4"))]
esp32,
esp_idf_version_major = "4",
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
impl<'d> embedded_hal_0_2::adc::OneShot<ADC1, u16, crate::hall::HallSensor> impl<'d> embedded_hal_0_2::adc::OneShot<ADC1, u16, crate::hall::HallSensor>
for AdcDriver<'d, ADC1> for AdcDriver<'d, ADC1>
{ {
@ -433,7 +412,6 @@ impl<'d> embedded_hal_0_2::adc::OneShot<ADC1, u16, crate::hall::HallSensor>
} }
} }
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
fn to_nb_err(err: EspError) -> nb::Error<EspError> { fn to_nb_err(err: EspError) -> nb::Error<EspError> {
if err.code() == ESP_ERR_INVALID_STATE { if err.code() == ESP_ERR_INVALID_STATE {
nb::Error::WouldBlock nb::Error::WouldBlock
@ -459,11 +437,7 @@ impl_adc!(ADC1: adc_unit_t_ADC_UNIT_1);
#[cfg(not(any(esp32c2, esp32h2, esp32c5, esp32c6, esp32p4)))] // TODO: Check for esp32c5 and esp32p4 #[cfg(not(any(esp32c2, esp32h2, esp32c5, esp32c6, esp32p4)))] // TODO: Check for esp32c5 and esp32p4
impl_adc!(ADC2: adc_unit_t_ADC_UNIT_2); impl_adc!(ADC2: adc_unit_t_ADC_UNIT_2);
#[cfg(all( #[cfg(all(not(esp_idf_version_major = "4"), esp_idf_comp_esp_adc_enabled))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(esp_idf_version_major = "4"),
esp_idf_comp_esp_adc_enabled
))]
pub mod oneshot { pub mod oneshot {
use core::borrow::Borrow; use core::borrow::Borrow;
@ -791,7 +765,6 @@ pub mod oneshot {
} }
#[cfg(all( #[cfg(all(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(esp_idf_version_major = "4"), not(esp_idf_version_major = "4"),
not(esp32c2), not(esp32c2),
esp_idf_comp_esp_adc_enabled esp_idf_comp_esp_adc_enabled

547
src/gpio.rs
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File diff suppressed because it is too large Load Diff

110
src/lib.rs
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@ -6,108 +6,53 @@
#![cfg_attr(feature = "nightly", feature(doc_cfg))] #![cfg_attr(feature = "nightly", feature(doc_cfg))]
#![cfg_attr(target_arch = "xtensa", feature(asm_experimental_arch))] #![cfg_attr(target_arch = "xtensa", feature(asm_experimental_arch))]
#[cfg(all(not(feature = "riscv-ulp-hal"), not(feature = "esp-idf-sys")))] #[cfg(not(esp_idf_comp_driver_enabled))]
compile_error!("Neither feature `esp-idf-sys`, nor feature `riscv-ulp-hal` is enabled");
#[cfg(all(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(esp_idf_comp_driver_enabled)
))]
compile_error!("esp-idf-hal requires the `driver` ESP-IDF component to be enabled"); compile_error!("esp-idf-hal requires the `driver` ESP-IDF component to be enabled");
#[cfg(all(
any(
feature = "std",
feature = "alloc",
feature = "critical-section-interrupt",
feature = "critical-section-mutex"
),
all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))
))]
compile_error!("Enabling feature `riscv-ulp-hal` implies no other feature is enabled");
#[cfg(all(
all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")),
not(esp32s2)
))]
compile_error!("Feature `riscv-ulp-hal` is currently only supported on esp32s2");
#[macro_use]
pub mod riscv_ulp_hal;
pub mod adc; pub mod adc;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod can; pub mod can;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod cpu; pub mod cpu;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod delay; pub mod delay;
pub mod gpio; pub mod gpio;
#[cfg(all(esp32, esp_idf_version_major = "4"))] #[cfg(all(esp32, esp_idf_version_major = "4"))]
pub mod hall; pub mod hall;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod i2c; pub mod i2c;
#[cfg(all(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_comp_driver_enabled
))]
#[cfg_attr( #[cfg_attr(
feature = "nightly", feature = "nightly",
doc(cfg(all(esp_idf_soc_i2s_supported, esp_idf_comp_driver_enabled))) doc(cfg(all(esp_idf_soc_i2s_supported, esp_idf_comp_driver_enabled)))
)] )]
pub mod i2s; pub mod i2s;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod interrupt; pub mod interrupt;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod io; pub mod io;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod ledc; pub mod ledc;
#[cfg(all( #[cfg(any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth))]
any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
pub mod mac; pub mod mac;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod modem; pub mod modem;
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pub mod pcnt; pub mod pcnt;
pub mod peripheral; pub mod peripheral;
pub mod peripherals; pub mod peripherals;
pub mod prelude; pub mod prelude;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod reset; pub mod reset;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod rmt; pub mod rmt;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod rom; pub mod rom;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod spi; pub mod spi;
pub mod sys; pub mod sys;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod task; pub mod task;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod timer; pub mod timer;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub mod uart; pub mod uart;
#[cfg(all( #[cfg(all(
any(esp32, esp32s2, esp32s3, esp32c6, esp32p4), any(esp32, esp32s2, esp32s3, esp32c6, esp32p4),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))) esp_idf_comp_ulp_enabled
))] ))]
pub mod ulp; pub mod ulp;
pub mod units; pub mod units;
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
pub use crate::riscv_ulp_hal::delay;
// This is used to create `embedded_hal` compatible error structs // This is used to create `embedded_hal` compatible error structs
// that preserve original `EspError`. // that preserve original `EspError`.
// //
// Example: // Example:
// embedded_hal_error!(I2cError, embedded_hal::i2c::Error, embedded_hal::i2c::ErrorKind) // embedded_hal_error!(I2cError, embedded_hal::i2c::Error, embedded_hal::i2c::ErrorKind)
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
#[allow(unused_macros)] #[allow(unused_macros)]
macro_rules! embedded_hal_error { macro_rules! embedded_hal_error {
($error:ident, $errortrait:ty, $kind:ty) => { ($error:ident, $errortrait:ty, $kind:ty) => {
@ -157,53 +102,6 @@ macro_rules! embedded_hal_error {
}; };
} }
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
#[allow(unused_macros)]
macro_rules! embedded_hal_error {
($error:ident, $errortrait:ty, $kind:ty) => {
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
pub struct $error {
kind: $kind,
cause: crate::riscv_ulp_hal::sys::EspError,
}
impl $error {
pub fn new(kind: $kind, cause: crate::riscv_ulp_hal::sys::EspError) -> Self {
Self { kind, cause }
}
pub fn other(cause: crate::riscv_ulp_hal::sys::EspError) -> Self {
Self::new(<$kind>::Other, cause)
}
pub fn cause(&self) -> crate::riscv_ulp_hal::sys::EspError {
self.cause
}
}
impl From<crate::riscv_ulp_hal::sys::EspError> for $error {
fn from(e: crate::riscv_ulp_hal::sys::EspError) -> Self {
Self::other(e)
}
}
impl $errortrait for $error {
fn kind(&self) -> $kind {
self.kind
}
}
impl core::fmt::Display for $error {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(
f,
"{} {{ kind: {}, cause: {} }}",
stringify!($error),
self.kind,
self.cause()
)
}
}
};
}
#[macro_export] #[macro_export]
#[allow(unused_macros)] #[allow(unused_macros)]
macro_rules! into_ref { macro_rules! into_ref {

288
src/peripherals.rs
View File

@ -1,208 +1,105 @@
use crate::adc; use crate::adc;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::can; use crate::can;
use crate::gpio; use crate::gpio;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::i2c; use crate::i2c;
#[cfg(all( #[cfg(esp_idf_soc_i2s_supported)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_soc_i2s_supported,
esp_idf_comp_driver_enabled
))]
use crate::i2s; use crate::i2s;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::ledc; use crate::ledc;
#[cfg(all( #[cfg(any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth))]
any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
use crate::mac; use crate::mac;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::modem; use crate::modem;
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
use crate::pcnt; use crate::pcnt;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::rmt; use crate::rmt;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::spi; use crate::spi;
#[cfg(all( #[cfg(any(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), all(
any( not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")),
all( esp_idf_esp_task_wdt_en
not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), ),
esp_idf_esp_task_wdt_en any(esp_idf_version_major = "4", esp_idf_version = "5.0")
),
any(esp_idf_version_major = "4", esp_idf_version = "5.0")
)
))] ))]
use crate::task::watchdog; use crate::task::watchdog;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::timer; use crate::timer;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
use crate::uart; use crate::uart;
#[cfg(all( #[cfg(all(
any(esp32, esp32s2, esp32s3, esp32c6, esp32p4), any(esp32, esp32s2, esp32s3, esp32c6, esp32p4),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_comp_ulp_enabled esp_idf_comp_ulp_enabled
))] ))]
use crate::ulp; use crate::ulp;
pub struct Peripherals { pub struct Peripherals {
pub pins: gpio::Pins, pub pins: gpio::Pins,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub uart0: uart::UART0, pub uart0: uart::UART0,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub uart1: uart::UART1, pub uart1: uart::UART1,
#[cfg(all( #[cfg(any(esp32, esp32s3))]
any(esp32, esp32s3),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
pub uart2: uart::UART2, pub uart2: uart::UART2,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub i2c0: i2c::I2C0, pub i2c0: i2c::I2C0,
#[cfg(all( #[cfg(not(any(esp32c3, esp32c2, esp32c6)))]
not(any(esp32c3, esp32c2, esp32c6)),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
pub i2c1: i2c::I2C1, pub i2c1: i2c::I2C1,
#[cfg(all( #[cfg(esp_idf_soc_i2s_supported)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_soc_i2s_supported,
esp_idf_comp_driver_enabled
))]
pub i2s0: i2s::I2S0, pub i2s0: i2s::I2S0,
#[cfg(all( #[cfg(all(esp_idf_soc_i2s_supported, any(esp32, esp32s3)))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_soc_i2s_supported,
esp_idf_comp_driver_enabled,
any(esp32, esp32s3)
))]
pub i2s1: i2s::I2S1, pub i2s1: i2s::I2S1,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub spi1: spi::SPI1, pub spi1: spi::SPI1,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub spi2: spi::SPI2, pub spi2: spi::SPI2,
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
any(esp32, esp32s2, esp32s3),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
pub spi3: spi::SPI3, pub spi3: spi::SPI3,
pub adc1: adc::ADC1, pub adc1: adc::ADC1,
#[cfg(any(esp32, esp32s2, esp32s3, esp32c3))] #[cfg(any(esp32, esp32s2, esp32s3, esp32c3))]
pub adc2: adc::ADC2, pub adc2: adc::ADC2,
// TODO: Check the pulse counter story for c2, h2, c5, c6, and p4 // TODO: Check the pulse counter story for c2, h2, c5, c6, and p4
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pub pcnt0: pcnt::PCNT0, pub pcnt0: pcnt::PCNT0,
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pub pcnt1: pcnt::PCNT1, pub pcnt1: pcnt::PCNT1,
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pub pcnt2: pcnt::PCNT2, pub pcnt2: pcnt::PCNT2,
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pub pcnt3: pcnt::PCNT3, pub pcnt3: pcnt::PCNT3,
#[cfg(all( #[cfg(esp32)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp32
))]
pub pcnt4: pcnt::PCNT4, pub pcnt4: pcnt::PCNT4,
#[cfg(all( #[cfg(esp32)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp32
))]
pub pcnt5: pcnt::PCNT5, pub pcnt5: pcnt::PCNT5,
#[cfg(all( #[cfg(esp32)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp32
))]
pub pcnt6: pcnt::PCNT6, pub pcnt6: pcnt::PCNT6,
#[cfg(all( #[cfg(esp32)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp32
))]
pub pcnt7: pcnt::PCNT7, pub pcnt7: pcnt::PCNT7,
#[cfg(all(esp32, esp_idf_version_major = "4"))] #[cfg(all(esp32, esp_idf_version_major = "4"))]
pub hall_sensor: crate::hall::HallSensor, pub hall_sensor: crate::hall::HallSensor,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub can: can::CAN, pub can: can::CAN,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub ledc: ledc::LEDC, pub ledc: ledc::LEDC,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub rmt: rmt::RMT, pub rmt: rmt::RMT,
#[cfg(all( #[cfg(all(
any(esp32, esp32s2, esp32s3, esp32c6, esp32p4), any(esp32, esp32s2, esp32s3, esp32c6, esp32p4),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_comp_ulp_enabled esp_idf_comp_ulp_enabled
))] ))]
pub ulp: ulp::ULP, pub ulp: ulp::ULP,
#[cfg(all( #[cfg(any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth))]
any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
pub mac: mac::MAC, pub mac: mac::MAC,
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub modem: modem::Modem, pub modem: modem::Modem,
// TODO: Check the timer story for c2, h2, c5, c6, and p4 // TODO: Check the timer story for c2, h2, c5, c6, and p4
#[cfg(all(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(feature = "embassy-time-isr-queue-timer00")
))]
pub timer00: timer::TIMER00, pub timer00: timer::TIMER00,
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
any(esp32, esp32s2, esp32s3),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(feature = "embassy-time-isr-queue-timer01")
))]
pub timer01: timer::TIMER01, pub timer01: timer::TIMER01,
#[cfg(all( #[cfg(not(esp32c2))]
not(esp32c2),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(feature = "embassy-time-isr-queue-timer10")
))]
pub timer10: timer::TIMER10, pub timer10: timer::TIMER10,
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
any(esp32, esp32s2, esp32s3),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(feature = "embassy-time-isr-queue-timer11")
))]
pub timer11: timer::TIMER11, pub timer11: timer::TIMER11,
#[cfg(all( #[cfg(any(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), all(
any( not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")),
all( esp_idf_esp_task_wdt_en
not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), ),
esp_idf_esp_task_wdt_en any(esp_idf_version_major = "4", esp_idf_version = "5.0")
),
any(esp_idf_version_major = "4", esp_idf_version = "5.0")
)
))] ))]
pub twdt: watchdog::TWDT, pub twdt: watchdog::TWDT,
} }
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
static mut TAKEN: bool = false;
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
static TAKEN: core::sync::atomic::AtomicBool = core::sync::atomic::AtomicBool::new(false); static TAKEN: core::sync::atomic::AtomicBool = core::sync::atomic::AtomicBool::new(false);
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
static TAKEN_CS: crate::task::CriticalSection = crate::task::CriticalSection::new(); static TAKEN_CS: crate::task::CriticalSection = crate::task::CriticalSection::new();
impl Peripherals { impl Peripherals {
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
pub fn take() -> Result<Self, crate::sys::EspError> { pub fn take() -> Result<Self, crate::sys::EspError> {
if unsafe { TAKEN } { if unsafe { TAKEN } {
panic!("Peripheral already taken") panic!("Peripheral already taken")
@ -214,7 +111,6 @@ impl Peripherals {
} }
} }
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub fn take() -> Result<Self, crate::sys::EspError> { pub fn take() -> Result<Self, crate::sys::EspError> {
if TAKEN.load(core::sync::atomic::Ordering::SeqCst) { if TAKEN.load(core::sync::atomic::Ordering::SeqCst) {
Err(crate::sys::EspError::from_infallible::< Err(crate::sys::EspError::from_infallible::<
@ -241,140 +137,66 @@ impl Peripherals {
pub unsafe fn new() -> Self { pub unsafe fn new() -> Self {
Self { Self {
pins: gpio::Pins::new(), pins: gpio::Pins::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
uart0: uart::UART0::new(), uart0: uart::UART0::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
uart1: uart::UART1::new(), uart1: uart::UART1::new(),
#[cfg(all( #[cfg(any(esp32, esp32s3))]
any(esp32, esp32s3),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
uart2: uart::UART2::new(), uart2: uart::UART2::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
i2c0: i2c::I2C0::new(), i2c0: i2c::I2C0::new(),
#[cfg(all( #[cfg(not(any(esp32c3, esp32c2, esp32c6)))]
not(any(esp32c3, esp32c2, esp32c6)),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
i2c1: i2c::I2C1::new(), i2c1: i2c::I2C1::new(),
#[cfg(all( #[cfg(esp_idf_soc_i2s_supported)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_soc_i2s_supported,
esp_idf_comp_driver_enabled
))]
i2s0: i2s::I2S0::new(), i2s0: i2s::I2S0::new(),
#[cfg(all( #[cfg(all(esp_idf_soc_i2s_supported, any(esp32, esp32s3)))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_soc_i2s_supported,
esp_idf_comp_driver_enabled,
any(esp32, esp32s3)
))]
i2s1: i2s::I2S1::new(), i2s1: i2s::I2S1::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
spi1: spi::SPI1::new(), spi1: spi::SPI1::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
spi2: spi::SPI2::new(), spi2: spi::SPI2::new(),
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
any(esp32, esp32s2, esp32s3),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
spi3: spi::SPI3::new(), spi3: spi::SPI3::new(),
adc1: adc::ADC1::new(), adc1: adc::ADC1::new(),
#[cfg(any(esp32, esp32s2, esp32s3, esp32c3))] #[cfg(any(esp32, esp32s2, esp32s3, esp32c3))]
adc2: adc::ADC2::new(), adc2: adc::ADC2::new(),
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pcnt0: pcnt::PCNT0::new(), pcnt0: pcnt::PCNT0::new(),
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pcnt1: pcnt::PCNT1::new(), pcnt1: pcnt::PCNT1::new(),
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pcnt2: pcnt::PCNT2::new(), pcnt2: pcnt::PCNT2::new(),
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
any(esp32, esp32s2, esp32s3)
))]
pcnt3: pcnt::PCNT3::new(), pcnt3: pcnt::PCNT3::new(),
#[cfg(all( #[cfg(esp32)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp32
))]
pcnt4: pcnt::PCNT4::new(), pcnt4: pcnt::PCNT4::new(),
#[cfg(all( #[cfg(esp32)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp32
))]
pcnt5: pcnt::PCNT5::new(), pcnt5: pcnt::PCNT5::new(),
#[cfg(all( #[cfg(esp32)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp32
))]
pcnt6: pcnt::PCNT6::new(), pcnt6: pcnt::PCNT6::new(),
#[cfg(all( #[cfg(esp32)]
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp32
))]
pcnt7: pcnt::PCNT7::new(), pcnt7: pcnt::PCNT7::new(),
#[cfg(all(esp32, esp_idf_version_major = "4"))] #[cfg(all(esp32, esp_idf_version_major = "4"))]
hall_sensor: crate::hall::HallSensor::new(), hall_sensor: crate::hall::HallSensor::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
can: can::CAN::new(), can: can::CAN::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
ledc: ledc::LEDC::new(), ledc: ledc::LEDC::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
rmt: rmt::RMT::new(), rmt: rmt::RMT::new(),
#[cfg(all( #[cfg(all(
any(esp32, esp32s2, esp32s3, esp32c6, esp32p4), any(esp32, esp32s2, esp32s3, esp32c6, esp32p4),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
esp_idf_comp_ulp_enabled esp_idf_comp_ulp_enabled
))] ))]
ulp: ulp::ULP::new(), ulp: ulp::ULP::new(),
#[cfg(all( #[cfg(any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth))]
any(all(esp32, esp_idf_eth_use_esp32_emac), esp_idf_eth_use_openeth),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))
))]
mac: mac::MAC::new(), mac: mac::MAC::new(),
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
modem: modem::Modem::new(), modem: modem::Modem::new(),
#[cfg(all(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(feature = "embassy-time-isr-queue-timer00")
))]
timer00: timer::TIMER00::new(), timer00: timer::TIMER00::new(),
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
any(esp32, esp32s2, esp32s3),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(feature = "embassy-time-isr-queue-timer01")
))]
timer01: timer::TIMER01::new(), timer01: timer::TIMER01::new(),
#[cfg(all( #[cfg(not(esp32c2))]
not(esp32c2),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(feature = "embassy-time-isr-queue-timer10")
))]
timer10: timer::TIMER10::new(), timer10: timer::TIMER10::new(),
#[cfg(all( #[cfg(any(esp32, esp32s2, esp32s3))]
any(esp32, esp32s2, esp32s3),
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))),
not(feature = "embassy-time-isr-queue-timer11")
))]
timer11: timer::TIMER11::new(), timer11: timer::TIMER11::new(),
#[cfg(all( #[cfg(any(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), all(
any( not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")),
all( esp_idf_esp_task_wdt_en
not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), ),
esp_idf_esp_task_wdt_en any(esp_idf_version_major = "4", esp_idf_version = "5.0")
),
any(esp_idf_version_major = "4", esp_idf_version = "5.0")
)
))] ))]
twdt: watchdog::TWDT::new(), twdt: watchdog::TWDT::new(),
} }

12
src/riscv_ulp_hal.rs
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@ -1,12 +0,0 @@
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
mod pac;
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
mod reg;
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
#[macro_use]
pub mod sys;
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
pub mod delay;
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
pub mod start;

57
src/riscv_ulp_hal/delay.rs
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@ -1,57 +0,0 @@
use super::sys::*;
/// Busy-loop based delay for the RiscV ULP coprocessor
pub struct Ulp;
impl embedded_hal_0_2::blocking::delay::DelayUs<u32> for Ulp {
fn delay_us(&mut self, us: u32) {
delay_cycles(us * ULP_RISCV_CYCLES_PER_US_NUM / ULP_RISCV_CYCLES_PER_US_DENUM);
}
}
impl embedded_hal_0_2::blocking::delay::DelayUs<u16> for Ulp {
fn delay_us(&mut self, us: u16) {
delay_cycles(us as u32 * ULP_RISCV_CYCLES_PER_US_NUM / ULP_RISCV_CYCLES_PER_US_DENUM);
}
}
impl embedded_hal_0_2::blocking::delay::DelayUs<u8> for Ulp {
fn delay_us(&mut self, us: u8) {
delay_cycles(us as u32 * ULP_RISCV_CYCLES_PER_US_NUM / ULP_RISCV_CYCLES_PER_US_DENUM);
}
}
impl embedded_hal_0_2::blocking::delay::DelayMs<u32> for Ulp {
fn delay_ms(&mut self, ms: u32) {
delay_cycles(ms * ULP_RISCV_CYCLES_PER_MS);
}
}
impl embedded_hal_0_2::blocking::delay::DelayMs<u16> for Ulp {
fn delay_ms(&mut self, ms: u16) {
delay_cycles(ms as u32 * ULP_RISCV_CYCLES_PER_MS);
}
}
impl embedded_hal_0_2::blocking::delay::DelayMs<u8> for Ulp {
fn delay_ms(&mut self, ms: u8) {
delay_cycles(ms as u32 * ULP_RISCV_CYCLES_PER_MS);
}
}
impl embedded_hal::delay::DelayNs for Ulp {
fn delay_ns(&mut self, ns: u32) {
delay_cycles(ns * ULP_RISCV_CYCLES_PER_US_NUM / ULP_RISCV_CYCLES_PER_US_DENUM)
}
fn delay_ms(&mut self, ms: u32) {
delay_cycles(ms * ULP_RISCV_CYCLES_PER_MS)
}
}
#[inline(always)]
fn delay_cycles(cycles: u32) {
let start = get_ccount();
while get_ccount() - start < cycles { /* Wait */ }
}

66
src/riscv_ulp_hal/pac.rs
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#![allow(dead_code)]
/// This module is a manual translation of a bunch of C files from current ESP-IDF master (currently ESP32-S2 specific):
/// - https://github.com/espressif/esp-idf/blob/master/components/soc/esp32s2/include/soc/soc.h (a subset)
/// - https://github.com/espressif/esp-idf/blob/master/components/soc/esp32s2/include/soc/sens_reg.h (a subset)
/// - https://github.com/espressif/esp-idf/blob/master/components/soc/esp32s2/include/soc/rtc_io_reg.h (a subset)
use super::reg::bit;
pub const DR_REG_SENS_BASE: u32 = 0x3f408800;
pub const DR_REG_RTCIO_BASE: u32 = 0x3ff48400;
pub const DR_REG_RTCCNTL_BASE: u32 = 0x3f408000;
pub const RTC_CNTL_COCPU_CTRL_REG: u32 = DR_REG_RTCCNTL_BASE + 0x0100;
pub const RTC_CNTL_COCPU_DONE: u32 = bit(25);
pub const RTC_CNTL_COCPU_SHUT_RESET_EN: u32 = bit(22);
pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS: u32 = 0x000000FF;
pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V: u32 = 0xFF;
pub const RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S: u32 = 14;
pub const RTC_CNTL_STATE0_REG: u32 = DR_REG_RTCCNTL_BASE + 0x0018;
pub const RTC_CNTL_SW_CPU_INT: u32 = bit(0);
pub const RTC_CNTL_ULP_CP_SLP_TIMER_EN: u32 = bit(31);
pub const RTC_CNTL_ULP_CP_SLP_TIMER_EN_V: u32 = 0x1;
pub const RTC_CNTL_ULP_CP_SLP_TIMER_EN_S: u32 = 31;
pub const SENS_SAR_IO_MUX_CONF_REG: u32 = DR_REG_SENS_BASE + 0x0144;
pub const SENS_IOMUX_CLK_GATE_EN_M: u32 = bit(31);
pub const RTC_IO_TOUCH_PAD0_REG: u32 = DR_REG_RTCIO_BASE + 0x84;
pub const RTC_IO_TOUCH_PAD0_DRV: u32 = 0x00000003;
pub const RTC_IO_TOUCH_PAD0_DRV_V: u32 = 0x3;
pub const RTC_IO_TOUCH_PAD0_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD0_MUX_SEL: u32 = bit(19);
pub const RTC_IO_TOUCH_PAD0_FUN_SEL: u32 = 0x00000003;
pub const RTC_IO_TOUCH_PAD0_FUN_SEL_V: u32 = 0x3;
pub const RTC_IO_TOUCH_PAD0_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD0_FUN_IE: u32 = bit(13);
pub const RTC_IO_TOUCH_PAD0_FUN_IE_V: u32 = 0x01;
pub const RTC_IO_TOUCH_PAD0_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD0_RUE: u32 = bit(27);
pub const RTC_IO_TOUCH_PAD0_RDE: u32 = bit(28);
pub const RTC_GPIO_ENABLE_W1TS_REG: u32 = DR_REG_RTCIO_BASE + 0x10;
pub const RTC_GPIO_ENABLE_W1TS: u32 = 0x0003FFFF;
pub const RTC_GPIO_ENABLE_W1TS_V: u32 = 0x3FFFF;
pub const RTC_GPIO_ENABLE_W1TS_S: u32 = 10;
pub const RTC_GPIO_ENABLE_W1TC_REG: u32 = DR_REG_RTCIO_BASE + 0x14;
pub const RTC_GPIO_ENABLE_W1TC: u32 = 0x0003FFFF;
pub const RTC_GPIO_ENABLE_W1TC_V: u32 = 0x3FFFF;
pub const RTC_GPIO_ENABLE_W1TC_S: u32 = 10;
pub const RTC_GPIO_IN_REG: u32 = DR_REG_RTCIO_BASE + 0x24;
pub const RTC_GPIO_IN_NEXT: u32 = 0x0003FFFF;
pub const RTC_GPIO_IN_NEXT_V: u32 = 0x3FFFF;
pub const RTC_GPIO_IN_NEXT_S: u32 = 10;
pub const RTC_GPIO_OUT_W1TS_REG: u32 = DR_REG_RTCIO_BASE + 0x4;
pub const RTC_GPIO_OUT_DATA_W1TS: u32 = 0x0003FFFF;
pub const RTC_GPIO_OUT_DATA_W1TS_V: u32 = 0x3FFFF;
pub const RTC_GPIO_OUT_DATA_W1TS_S: u32 = 10;
pub const RTC_GPIO_OUT_W1TC_REG: u32 = DR_REG_RTCIO_BASE + 0x8;
pub const RTC_GPIO_OUT_DATA_W1TC: u32 = 0x0003FFFF;
pub const RTC_GPIO_OUT_DATA_W1TC_V: u32 = 0x3FFFF;
pub const RTC_GPIO_OUT_DATA_W1TC_S: u32 = 10;

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src/riscv_ulp_hal/reg.rs
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#![allow(dead_code)]
/// This module is a manual translation of the following C file from current ESP-IDF master:
/// - https://github.com/espressif/esp-idf/blob/master/components/ulp/ulp_riscv/include/ulp_riscv/ulp_riscv_register_ops.h
use core::ptr::{read_volatile, write_volatile};
/*
* When COCPU accesses the RTC register, it needs to convert the access address.
* When COCPU accesses the RTC memory, dont need to convert the access address.
*/
#[inline(always)]
pub unsafe fn write_rtc_mem(addr: u32, val: i32) {
write_volatile(addr as *mut i32, val);
}
#[inline(always)]
pub unsafe fn read_rtc_mem(addr: u32) -> i32 {
read_volatile(addr as *const i32)
}
/*
* When COCPU accesses the RTC register, it needs to convert the access address.
* When COCPU accesses the RTC memory, dont need to convert the access address.
*/
#[inline(always)]
pub const fn riscv_reg_conv(addr: u32) -> u32 {
((addr & 0xffff) << 3) & 0xe000 | addr & 0x1fff | 0x8000
}
#[inline(always)]
pub const fn ets_uncached_addr(addr: u32) -> u32 {
riscv_reg_conv(addr)
}
#[inline(always)]
pub const fn bit(nr: u32) -> u32 {
1u32 << nr
}
// Write value to register
#[inline(always)]
pub unsafe fn reg_write(r: u32, v: u32) {
write_volatile(riscv_reg_conv(r) as *mut u32, v);
}
// Read value from register
#[inline(always)]
pub unsafe fn reg_read(r: u32) -> u32 {
read_volatile(riscv_reg_conv(r) as *const u32)
}
// Get bit or get bits from register
#[inline(always)]
pub unsafe fn reg_get_bit(r: u32, b: u32) -> u32 {
read_volatile(riscv_reg_conv(r) as *const u32) & b
}
// Get bit or get bits from register
#[inline(always)]
pub unsafe fn reg_set_bit(r: u32, b: u32) {
let addr = riscv_reg_conv(r) as *mut u32;
write_volatile(addr, read_volatile(addr) | b);
}
// Clear bit or clear bits of register
#[inline(always)]
pub unsafe fn reg_clr_bit(r: u32, b: u32) {
let addr = riscv_reg_conv(r) as *mut u32;
write_volatile(addr, read_volatile(addr) & !b);
}
// Set bits of register controlled by mask
#[inline(always)]
pub unsafe fn reg_set_bits(r: u32, b: u32, m: u32) {
let addr = riscv_reg_conv(r) as *mut u32;
write_volatile(addr, read_volatile(addr) & !m | b & m);
}
// Get field from register, uses field _S & _V to determine mask
#[inline(always)]
pub unsafe fn reg_get_field(r: u32, f_s: u32, f_v: u32) -> u32 {
(reg_read(r) >> f_s) & f_v
}
// Set field of a register from variable, uses field _S & _V to determine mask
#[inline(always)]
pub unsafe fn reg_set_field(r: u32, f_s: u32, f_v: u32, v: u32) {
reg_write(r, (reg_read(r) & !(f_v << f_s)) | ((v & f_v) << f_s));
}
// Get field value from a variable, used when _f is not left shifted by _f##_S
#[inline(always)]
pub const fn value_get_field(r: u32, f: u32, f_s: u32) -> u32 {
(r >> f_s) & f
}
// Get field value from a variable, used when _f is left shifted by _f##_S
#[inline(always)]
pub const fn value_get_field2(r: u32, f: u32, f_s: u32) -> u32 {
(r & f) >> f_s
}
// Set field value to a variable, used when _f is not left shifted by _f##_S
#[inline(always)]
pub const fn value_set_field(r: u32, f: u32, f_s: u32, v: u32) -> u32 {
r & !(f << f_s) | (v << f_s)
}
// Set field value to a variable, used when _f is left shifted by _f##_S
#[inline(always)]
pub const fn value_set_field2(r: u32, f: u32, f_s: u32, v: u32) -> u32 {
r & !f | (v << f_s)
}
// Generate a value from a field value, used when _f is not left shifted by _f##_S
#[inline(always)]
pub const fn field_to_value(f: u32, f_s: u32, v: u32) -> u32 {
(v & f) << f_s
}
// Generate a value from a field value, used when _f is left shifted by _f##_S
#[inline(always)]
pub const fn field_to_value2(f: u32, f_s: u32, v: u32) -> u32 {
(v << f_s) & f
}
// Read value from register
#[inline(always)]
pub unsafe fn read_peri_reg(addr: u32) -> u32 {
read_volatile(ets_uncached_addr(addr) as *const u32)
}
// Write value to register
#[inline(always)]
pub unsafe fn write_peri_reg(addr: u32, v: u32) {
write_volatile(ets_uncached_addr(addr) as *mut u32, v);
}
// Clear bits of register controlled by mask
#[inline(always)]
pub unsafe fn clear_peri_reg_mask(addr: u32, mask: u32) {
write_peri_reg(addr, read_peri_reg(addr) & !mask);
}
#[inline(always)]
pub unsafe fn set_peri_reg_mask(addr: u32, mask: u32) {
write_peri_reg(addr, read_peri_reg(addr) | mask);
}
// Get bits of register controlled by mask
#[inline(always)]
pub unsafe fn get_peri_reg_mask(addr: u32, mask: u32) -> u32 {
read_peri_reg(addr) & mask
}
// Get bits of register controlled by highest bit and lowest bit
#[inline(always)]
pub unsafe fn get_peri_reg_bits(addr: u32, bit_map: u32, shift: u8) -> u32 {
(read_peri_reg(addr) & (bit_map << shift)) >> shift
}
// Set bits of register controlled by mask and shift
pub unsafe fn set_peri_reg_bits(addr: u32, bit_map: u32, value: u32, shift: u8) {
write_peri_reg(
addr,
read_peri_reg(addr) & !(bit_map << shift) | ((value & bit_map) << shift),
);
}
// Get field of register
pub unsafe fn get_peri_reg_bits2(addr: u32, mask: u32, shift: u8) -> u32 {
(read_peri_reg(addr) >> shift) & mask
}

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src/riscv_ulp_hal/start.rs
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@ -1,179 +0,0 @@
//! Minimal startup / runtime for ESP32-SXX RISC-V ULPs
//! Adapted from riscv-rt/src/lib.rs
#![deny(missing_docs)]
use super::sys::cpu;
#[export_name = "error: ulp_start appears more than once in the dependency graph"]
#[doc(hidden)]
pub static __ONCE__: () = ();
/// # Safety
///
/// Rust entry point (_start_rust)
/// This function is NOT supposed to be called from use code
///
/// Calls main. This function never returns.
#[link_section = ".start.rust"]
#[export_name = "_start_rust"]
pub unsafe extern "C" fn start_rust() -> ! {
#[rustfmt::skip]
extern "Rust" {
// This symbol will be provided by the user
fn main();
}
cpu::rescue_from_monitor();
main();
cpu::shutdown();
}
/// Registers saved in trap handler
#[allow(missing_docs)]
#[repr(C)]
pub struct TrapFrame {
pub ra: usize,
pub t0: usize,
pub t1: usize,
pub t2: usize,
pub t3: usize,
pub t4: usize,
pub t5: usize,
pub t6: usize,
pub a0: usize,
pub a1: usize,
pub a2: usize,
pub a3: usize,
pub a4: usize,
pub a5: usize,
pub a6: usize,
pub a7: usize,
}
/// # Safety
///
/// Trap entry point rust (_start_trap_rust)
/// This function is NOT supposed to be called from use code
///
/// `mcause` is read to determine the cause of the trap. XLEN-1 bit indicates
/// if it's an interrupt or an exception. The result is examined and ExceptionHandler
/// or one of the core interrupt handlers is called.
#[link_section = ".trap.rust"]
#[export_name = "_start_trap_rust"]
pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
// use riscv::register::mcause;
extern "C" {
fn ExceptionHandler(trap_frame: &TrapFrame);
#[allow(dead_code)]
fn DefaultHandler();
}
// let cause = mcause::read();
// if cause.is_exception() {
ExceptionHandler(trap_frame.as_ref().unwrap())
// } else {
// let code = cause.code();
// if code < __INTERRUPTS.len() {
// let h = &__INTERRUPTS[code];
// if h.reserved == 0 {
// DefaultHandler();
// } else {
// (h.handler)();
// }
// } else {
// DefaultHandler();
// }
// }
}
#[doc(hidden)]
#[no_mangle]
#[allow(unused_variables, non_snake_case)]
pub fn DefaultExceptionHandler(trap_frame: &TrapFrame) -> ! {
loop {
// Prevent this from turning into a UDF instruction
// see rust-lang/rust#28728 for details
continue;
}
}
#[doc(hidden)]
#[no_mangle]
#[allow(unused_variables, non_snake_case)]
pub fn DefaultInterruptHandler() {
loop {
// Prevent this from turning into a UDF instruction
// see rust-lang/rust#28728 for details
continue;
}
}
/* Interrupts */
#[doc(hidden)]
pub enum Interrupt {
UserSoft,
SupervisorSoft,
MachineSoft,
UserTimer,
SupervisorTimer,
MachineTimer,
UserExternal,
SupervisorExternal,
MachineExternal,
}
pub use self::Interrupt as interrupt;
extern "C" {
fn UserSoft();
fn SupervisorSoft();
fn MachineSoft();
fn UserTimer();
fn SupervisorTimer();
fn MachineTimer();
fn UserExternal();
fn SupervisorExternal();
fn MachineExternal();
}
#[doc(hidden)]
pub union Vector {
handler: unsafe extern "C" fn(),
reserved: usize,
}
#[doc(hidden)]
#[allow(dead_code)]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 12] = [
Vector { handler: UserSoft },
Vector {
handler: SupervisorSoft,
},
Vector { reserved: 0 },
Vector {
handler: MachineSoft,
},
Vector { handler: UserTimer },
Vector {
handler: SupervisorTimer,
},
Vector { reserved: 0 },
Vector {
handler: MachineTimer,
},
Vector {
handler: UserExternal,
},
Vector {
handler: SupervisorExternal,
},
Vector { reserved: 0 },
Vector {
handler: MachineExternal,
},
];

28
src/riscv_ulp_hal/sys.rs
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@ -1,28 +0,0 @@
/// A mini "esp-idf-ulp-sys" module exposing stuff on top of which the ULP HAL support is implemented
/// (currently, only GPIO) + some utilities for the riscv ULP processor
pub use self::cpu::*;
pub use self::gpio::*;
pub mod cpu;
#[allow(clippy::missing_safety_doc)]
pub mod gpio;
pub type EspError = core::convert::Infallible;
#[macro_export]
macro_rules! esp_result {
($err:expr, $value:expr) => {{
$err;
Ok($value)
}};
}
#[macro_export]
macro_rules! esp {
($err:expr) => {{
$err;
core::result::Result::<(), EspError>::Ok(())
}};
}

71
src/riscv_ulp_hal/sys/cpu.rs
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@ -1,71 +0,0 @@
#![allow(dead_code)]
/// This module is a manual translation of the following C file from current ESP-IDF master:
/// - https://github.com/espressif/esp-idf/blob/master/components/ulp/ulp_riscv/include/ulp_riscv/ulp_utils.h
/// - https://github.com/espressif/esp-idf/blob/master/components/ulp/ulp_riscv/ulp_utils.c
use core::arch::asm;
use crate::riscv_ulp_hal::pac::*;
use crate::riscv_ulp_hal::reg::*;
pub const ULP_RISCV_CYCLES_PER_US_NUM: u32 = 85;
pub const ULP_RISCV_CYCLES_PER_US_DENUM: u32 = 10;
pub const ULP_RISCV_CYCLES_PER_MS: u32 =
ULP_RISCV_CYCLES_PER_US_NUM * (1000 / ULP_RISCV_CYCLES_PER_US_DENUM);
#[inline(always)]
pub fn get_ccount() -> u32 {
#[allow(unused_assignments)]
let mut ccount = 0;
unsafe {
asm!("rdcycle {}", out(reg) ccount);
}
ccount
}
pub fn wakeup_main_processor() {
unsafe { set_peri_reg_mask(RTC_CNTL_STATE0_REG, RTC_CNTL_SW_CPU_INT) };
}
pub fn rescue_from_monitor() {
// Rescue RISCV from monitor state
unsafe {
clear_peri_reg_mask(
RTC_CNTL_COCPU_CTRL_REG,
RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN,
)
};
}
pub fn enable_timer(enable: bool) {
unsafe {
if enable {
set_peri_reg_mask(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
} else {
clear_peri_reg_mask(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
}
}
}
pub fn shutdown() -> ! {
unsafe {
// Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time.
reg_set_field(
RTC_CNTL_COCPU_CTRL_REG,
RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S,
RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V,
0x3F,
);
// Suspends the ulp operation
set_peri_reg_mask(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
// Resets the processor
set_peri_reg_mask(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
}
#[allow(clippy::empty_loop)]
loop {}
}

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/// A mini "esp-idf-ulp-sys" module exposing stuff on top of which the ULP HAL support is implemented
/// (currently, only GPIO)
/// Implemented as a manual transation of a few C fields from current ESP-IDF S2 master:
/// - https://github.com/espressif/esp-idf/blob/master/components/ulp/ulp_riscv/include/ulp_riscv/ulp_riscv_gpio.h
use crate::riscv_ulp_hal::pac::*;
use crate::riscv_ulp_hal::reg::*;
#[allow(non_camel_case_types)]
pub type adc_unit_t = i32;
#[allow(non_camel_case_types)]
pub type adc_channel_t = i32;
#[allow(non_camel_case_types)]
pub type dac_channel_t = i32;
#[allow(non_camel_case_types)]
pub type touch_pad_t = i32;
#[allow(non_camel_case_types)]
pub type adc_atten_t = i32;
#[allow(non_camel_case_types)]
pub type gpio_mode_t = u8;
#[allow(non_camel_case_types)]
pub type gpio_pull_mode_t = u8;
#[allow(non_upper_case_globals)]
pub const adc_unit_t_ADC_UNIT_1: adc_unit_t = 0;
#[allow(non_upper_case_globals)]
pub const adc_unit_t_ADC_UNIT_2: adc_unit_t = 1;
#[allow(non_upper_case_globals)]
pub const adc_atten_t_ADC_ATTEN_DB_0: adc_atten_t = 0;
#[allow(non_upper_case_globals)]
pub const adc_atten_t_ADC_ATTEN_DB_2_5: adc_atten_t = 1;
#[allow(non_upper_case_globals)]
pub const adc_atten_t_ADC_ATTEN_DB_6: adc_atten_t = 2;
#[allow(non_upper_case_globals)]
pub const adc_atten_t_ADC_ATTEN_DB_11: adc_atten_t = 3;
#[allow(non_upper_case_globals)]
pub const gpio_mode_t_GPIO_MODE_DISABLE: u8 = 0;
#[allow(non_upper_case_globals)]
pub const gpio_mode_t_GPIO_MODE_INPUT: u8 = 1;
#[allow(non_upper_case_globals)]
pub const gpio_mode_t_GPIO_MODE_OUTPUT: u8 = 2;
#[allow(non_upper_case_globals)]
pub const gpio_mode_t_GPIO_MODE_INPUT_OUTPUT: u8 = 3;
#[allow(non_upper_case_globals)]
pub const gpio_mode_t_GPIO_MODE_OUTPUT_OD: u8 = 4;
#[allow(non_upper_case_globals)]
pub const gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD: u8 = 5;
#[allow(non_upper_case_globals)]
pub const gpio_pull_mode_t_GPIO_PULLUP_ONLY: u8 = 0;
#[allow(non_upper_case_globals)]
pub const gpio_pull_mode_t_GPIO_PULLDOWN_ONLY: u8 = 1;
#[allow(non_upper_case_globals)]
pub const gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN: u8 = 2;
#[allow(non_upper_case_globals)]
pub const gpio_pull_mode_t_GPIO_FLOATING: u8 = 3;
#[inline(always)]
pub unsafe fn gpio_set_direction(gpio_num: i32, direction: u8) {
if direction == gpio_mode_t_GPIO_MODE_DISABLE {
// Deinit
clear_peri_reg_mask(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_MUX_SEL,
);
return;
} else {
// Init
set_peri_reg_mask(SENS_SAR_IO_MUX_CONF_REG, SENS_IOMUX_CLK_GATE_EN_M);
set_peri_reg_mask(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_MUX_SEL,
);
reg_set_field(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_FUN_SEL_S,
RTC_IO_TOUCH_PAD0_FUN_SEL_V,
0,
);
}
let input = direction == gpio_mode_t_GPIO_MODE_INPUT
|| direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT
|| direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD;
let output = direction == gpio_mode_t_GPIO_MODE_OUTPUT
|| direction == gpio_mode_t_GPIO_MODE_OUTPUT_OD
|| direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT
|| direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD;
let od = direction == gpio_mode_t_GPIO_MODE_OUTPUT_OD
|| direction == gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD;
if input {
set_peri_reg_mask(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_FUN_IE,
);
} else {
clear_peri_reg_mask(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_FUN_IE,
);
}
if output {
reg_set_field(
RTC_GPIO_ENABLE_W1TS_REG,
RTC_GPIO_ENABLE_W1TS_S,
RTC_GPIO_ENABLE_W1TS_V,
bit(gpio_num as u32),
);
reg_set_field(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_DRV_S,
RTC_IO_TOUCH_PAD0_DRV_V,
if od { 1 } else { 0 },
);
} else {
reg_set_field(
RTC_GPIO_ENABLE_W1TC_REG,
RTC_GPIO_ENABLE_W1TC_S,
RTC_GPIO_ENABLE_W1TC_V,
bit(gpio_num as u32),
);
}
}
#[inline(always)]
pub unsafe fn gpio_set_pull_mode(gpio_num: i32, mode: u8) {
let pullup =
mode == gpio_pull_mode_t_GPIO_PULLUP_ONLY || mode == gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN;
let pulldown = mode == gpio_pull_mode_t_GPIO_PULLDOWN_ONLY
|| mode == gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN;
if pullup {
set_peri_reg_mask(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_RUE,
);
} else {
clear_peri_reg_mask(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_RUE,
);
}
if pulldown {
set_peri_reg_mask(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_RDE,
);
} else {
clear_peri_reg_mask(
RTC_IO_TOUCH_PAD0_REG + gpio_num as u32 * 4,
RTC_IO_TOUCH_PAD0_RDE,
);
}
}
#[inline(always)]
pub unsafe fn gpio_get_level(gpio_num: i32) -> u8 {
if (reg_get_field(RTC_GPIO_IN_REG, RTC_GPIO_IN_NEXT_S, RTC_GPIO_IN_NEXT_V)
& bit(gpio_num as u32))
!= 0
{
1
} else {
0
}
}
#[inline(always)]
pub unsafe fn gpio_set_level(gpio_num: i32, level: u8) {
if level != 0 {
reg_set_field(
RTC_GPIO_OUT_W1TS_REG,
RTC_GPIO_OUT_DATA_W1TS_S,
RTC_GPIO_OUT_DATA_W1TS_V,
bit(gpio_num as u32),
);
} else {
reg_set_field(
RTC_GPIO_OUT_W1TC_REG,
RTC_GPIO_OUT_DATA_W1TC_S,
RTC_GPIO_OUT_DATA_W1TC_V,
bit(gpio_num as u32),
);
}
}
#[inline(always)]
pub unsafe fn gpio_get_output_level(gpio_num: i32) -> u8 {
if (reg_get_field(
RTC_GPIO_OUT_W1TS_REG,
RTC_GPIO_OUT_DATA_W1TS_S,
RTC_GPIO_OUT_DATA_W1TS_V,
) & bit(gpio_num as u32))
!= 0
{
1
} else {
0
}
}

4
src/sys.rs
View File

@ -1,5 +1 @@
#[cfg(not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))))]
pub use esp_idf_sys::*; pub use esp_idf_sys::*;
#[cfg(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys")))]
pub use crate::riscv_ulp_hal::sys::*;

15
src/task.rs
View File

@ -487,15 +487,12 @@ impl<'a> Drop for CriticalSectionGuard<'a> {
} }
} }
#[cfg(all( #[cfg(any(
not(all(feature = "riscv-ulp-hal", not(feature = "esp-idf-sys"))), all(
any( not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")),
all( esp_idf_esp_task_wdt_en
not(any(esp_idf_version_major = "4", esp_idf_version = "5.0")), ),
esp_idf_esp_task_wdt_en any(esp_idf_version_major = "4", esp_idf_version = "5.0")
),
any(esp_idf_version_major = "4", esp_idf_version = "5.0")
)
))] ))]
pub mod watchdog { pub mod watchdog {
//! ## Example //! ## Example