1702 Commits

Author SHA1 Message Date
Folkert de Vries
a850e8738a avx512_target_feature is now stable on nightly 2025-05-20 14:26:46 +00:00
sayantn
806848f01e Correct rustc version for the stabilization of runtime detection of VEX variants of avx512 2025-05-17 17:43:54 +00:00
sayantn
98c4ba9783 Stabilize runtime detection of VEX variants of avx512 2025-05-17 09:48:33 +00:00
WANG Rui
63235a6ba5 Partially stabilize LoongArch target features 2025-05-12 19:47:49 +00:00
sayantn
546e26518f Run aarch64-pc-windows-msvc runs on the new windows-11-arm runners 2025-05-06 16:10:50 +00:00
sayantn
949fd567f3 Edit macro_trailing_commas to enable tests in all architectures 2025-05-06 16:10:50 +00:00
sayantn
b1ad50f1e0 Add riscv32 CI run 2025-05-06 16:10:50 +00:00
James Barford-Evans
206c35a3a2 change how the test is run 2025-05-03 05:06:15 +00:00
James Barford-Evans
052293b092 add printouts for debugging 2025-05-03 05:06:15 +00:00
James Barford-Evans
45ee41c13a pr feedback - take the instruction count bump out of Dockerfile 2025-05-03 05:06:15 +00:00
James Barford-Evans
c65583c2b3 Pr feedback for instruction & hookup CI for aarch64_be 2025-05-03 05:06:15 +00:00
James Barford-Evans
ef92b59242 fix - aarch64_be tests 2025-05-03 05:06:15 +00:00
sayantn
f8782f778b Fix errors in incorrect SAE and ROUNDING parameters 2025-05-03 05:03:31 +00:00
sayantn
4d665d1a01 Require fma and f16c for avx512f in std_detect 2025-05-01 11:37:00 +00:00
sayantn
ed25a9bde4 Implement sha512, sm3 and sm4 intrinsics 2025-05-01 11:30:47 +00:00
sayantn
400dab3df7 Fix stdarch-verify 2025-05-01 11:30:47 +00:00
Tsukasa OI
50010d5546 Revert "std_detect: RISC-V platform guide documentation"
This reverts commit e907456b2e10622ccd854a3bba8d02ce170b5dbb.

This is due to a CI failure (technically broken HTML with duplicate IDs)
caused by this commit (visibly fine but invalid per the HTML specification
and detected by the LinkCheck tool on the Rust CI process).

The author independently working on a rustdoc enhancement to enable writing
multiple references to a single footnote.  Once that change makes it to the
stage0 compiler (the next beta), the original change will be acceptable
again (postponed for possibly the version 1.89 cycle).
2025-05-01 11:24:23 +00:00
sayantn
a21396870c Add avx512vl requirement to testsuite for avx512fp16 128 and 256 bit 2025-04-29 11:59:15 +00:00
sayantn
288ae22354 Fix errors in decoupling avx512vl and avx512dq from avx512fp16 2025-04-29 11:59:15 +00:00
sayantn
caf463ae41 Fix CI errors due to alignment issues in msvc 2025-04-29 11:59:15 +00:00
Tsukasa OI
7db430fb80 std_detect: RISC-V platform guide documentation
Since there's no architectural feature detection on RISC-V (unlike `CPUID`
on x86 architectures and some system registers on Arm/AArch64), runtime
feature detection entirely depends on the platform-specific facility.

As a result, availability of each feature heavily depends on the platform
and its version.

To help users make a decision for feature checking on a RISC-V system, this
commit adds a platform guide with minimum supported platform versions.

Note:

It intentionally omits the description of the reverse implication related
to *extension groups* (such like implication of `B` *from* its members:
`Zba`, `Zbb` and `Zbs` extensions) because it currently does not synchronize
well with the `-Ctarget-feature` compiler option (due to missing reverse
implication checks using `cfg` and due to constraints of the current Rust's
feature handling).

Instead, it only describes forward implications (like `D` implying `F`) due
to the fact that it relatively synchronizes well between Rust and `stdarch`
for this kind of feature handling (not fully synchronized though).

Still, an extension group is considered "supported" once the
platform/version supports runtime detection of all members in it.
2025-04-23 19:32:43 +00:00
sayantn
e61df091c1 Remove workarounds for llvm/llvm-project#98306 2025-04-23 10:40:09 +00:00
Luca Barbato
5fb4fabbfc Add power9 and power8 target-features 2025-04-23 10:38:58 +00:00
Folkert de Vries
f77386cf2b run powerpc64le assert_instr on CI 2025-04-23 10:38:19 +00:00
Ralf Jung
1e3c5e3c99 use 'unadjusted' ABI for wasm LLVM intrinsics 2025-04-21 17:59:41 +00:00
sayantn
421bf535b7 Augment stdarch-test to parse PPC
- Remove some unused env variables from `run.sh`
2025-04-20 21:39:39 +00:00
sayantn
867fe30ba0 Add test-everything annotations to more archs to ensure test coverage, and some small changes to make CI pass
- Disable `vsx` tests for `ppc` and `ppc64`
 - Disable `tme` tests for `aarch64` and `aarch64_be`
 - Disable `frecipe` tests for `loongarch64`
 - Add `altivec` run for PPC32 (with `-C target-feature=+vsx` `qemu` gives a nasty error)
2025-04-20 21:39:39 +00:00
sayantn
f2870b76fd Remove STDARCH_DISABLE_DEDUP_GUARD as it was unused 2025-04-20 21:39:39 +00:00
sayantn
bc9e29d9be Replace cfg(stdarch_intel_sde) with STDARCH_TEST_SKIP_FUNCTION 2025-04-20 21:39:39 +00:00
sayantn
b3a7ba4607 Change test skipping logic a little, separate feature-based and function-based skipping 2025-04-20 21:39:39 +00:00
sayantn
cc6855e1e9 Remove cupid dependency and env-override-no-avx CI run 2025-04-20 21:39:39 +00:00
sayantn
6cc17153d9 Re-enable all conditionally-disabled x86 assert_instr tests 2025-04-20 21:39:39 +00:00
Taiki Endo
4621641a49 std_detect: Remove /proc/cpuinfo-based detection 2025-04-20 14:38:01 +00:00
bendn
3dd82b698f allow unnecessary transmutes 2025-04-17 18:27:37 +00:00
Folkert de Vries
c899659c44 add vec_extract, vec_insert, vec_promote and vec_insert_and_zero 2025-04-17 17:06:09 +00:00
sayantn
e804386587 Change void* type for gather/scatter intrinsics 2025-04-17 13:59:07 +00:00
sayantn
d6b0426127 Change void* type for cvt_storeu intrinsics 2025-04-17 13:59:07 +00:00
sayantn
376c3f33c5 Change void* type for compressstore intrinsics 2025-04-17 13:59:07 +00:00
sayantn
b10a6817d9 Change void* type for 3 intrinsics
- `_mm512_load_si512`
 - `_mm512_loadu_si512`
 - `_mm512_stream_si512`
2025-04-17 13:59:07 +00:00
sayantn
ccf36667b0 Add checks for void pointer types to ensure consistency 2025-04-17 13:59:07 +00:00
Taiki Endo
8f30830d97 Revert "std_detect: Do not use libc::getauxval on 32-bit Android"
This reverts commit 85572dc298f5222902c9b200cebf5d045e769a83.
2025-04-16 19:43:08 +00:00
Tsukasa OI
2d2390ea39 std_detect: Remove RV32E support attempt on Linux (RISC-V)
Because the current lowest requirements to run the Linux kernel on RISC-V is
RV{32,64}IMA (with 32 general purpose registers) plus some features,
RV32E (with only 16 GPRs) is not currently supported.

Since it's not sure whether current implemented method will work for future
Linux versions even if the minimum requirements are lowered, the support for
RV32E (to be more specific, an attempt to do that) is removed for now.
2025-04-16 18:30:32 +00:00
Tsukasa OI
ceaeba1760 RISC-V: Remove privileged extensions for now
Until in-kernel feature detection is implemented, runtime detection of
privileged extensions is temporally removed along with features themselves
since none of such privileged features are stable.

Co-Authored-By: Taiki Endo <te316e89@gmail.com>
Co-Authored-By: Amanieu d'Antras <amanieu@gmail.com>
2025-04-16 00:56:48 +00:00
Tsukasa OI
d5baf4da91 RISC-V: riscv_hwprobe-based feature detection on Linux / Android
This commit implements `riscv_hwprobe`-based feature detection as available
on newer versions of the Linux kernel.  It also queries whether the vector
extensions are enabled using `prctl` but this is not supported on QEMU's
userland emulator (as of version 9.2.3) and use the auxiliary vector
as a fallback.

Currently, all extensions discoverable from the Linux kernel version 6.14
and related extension groups (except "Supm", which reports the existence of
`prctl`-based pointer masking control and too OS-dependent) are implemented.

Co-Authored-By: Taiki Endo <te316e89@gmail.com>
2025-04-16 00:56:48 +00:00
Tsukasa OI
db188b33b3 RISC-V: OS-independent implication logic
This commit adds the OS-independent extension implication logic for RISC-V.
It implements:

1.  Regular implication (A → B)
    a.  "the extension A implies the extension B"
    b.  "the extension A requires the extension B"
    c.  "the extension A depends on the extension B"
2.  Extension group or shorthand (A == B1 & B2...)
    a.  "the extension A is shorthand for other extensions: B1, B2..."
    b.  "the extension A comprises instructions provided by B1, B2..."
    This is implemented as (A → B1 & B2... + B1 & B2... → A)
    where the former is a regular implication as required by specifications
    and the latter is a "reverse" implication to improve usability.

and prepares for:

3.  Implication with multiple requirements (A1 & A2... → B)
    a.  "A1 + A2 implies B"
    b.  (implicitly used to implement reverse implication of case 2)

Although it uses macros and iterators, good optimizers turn the series of
implications into fast bit-manipulation operations.

In the case 2 (extension group or shorthand; where a superset extension
is just a collection of other subextensions and provides no features by
a superset itself), specifications do specify that an extension group
implies its members but not vice versa.  However, implying an extension
group from its members would improve usability on the feature detection
(especially when the feature provider does not provide existence of such
extension group but provides existence of its members).

Similar "reverse implication" on RISC-V is implemented on LLVM.

Case 3 is implicitly used to implement reverse implication of case 2 but
there's another use case: implication with multiple requirements like
"Zcf" and "Zcd" extensions (not yet implemented in this crate for now).

To handle extension groups perfectly, we need to loop implication several
times (until they converge; normally 2 times and up to 4 times when we add
most of `riscv_hwprobe`-based features).
To make implementation of that loop possible, `cache::Initializer` is
modified to implement `PartialEq` and `Eq`.
2025-04-16 00:56:48 +00:00
Tsukasa OI
de643c040d RISC-V: Add RISC-V + Linux / Android test
This is ported from Taiki Endo's branch and sorted by the `@FEATURE` order
as in `src/detect/arch/riscv.rs`.

Co-Authored-By: Taiki Endo <te316e89@gmail.com>
2025-04-16 00:56:48 +00:00
Tsukasa OI
ed2d3ee924 RISC-V: Add placeholder for the "B" extension
The "B" extension is once abandoned (instead, it is ratified as a collection
of "Zb*" extensions).  However, it is later redefined and ratified as a
superset of "Zba", "Zbb" and "Zbs" extensions (but not "Zbc" carry-less
multiplication for limited benefits and implementation cost).

Although non-functional (because feature detection is not yet implemented),
it provides the foundation to implement this extension (along with
straightforward documentation showing subsets of "B").
2025-04-16 00:56:48 +00:00
Tsukasa OI
68c54c19be RISC-V: Add two "A" extension subsets
The "A" extension comprises instructions provided by the "Zaamo" and
"Zalrsc" extensions.  To prepare for the "Zacas" extension (which provides
compare-and-swap instructions and discoverable from Linux) which depends on
the "Zaamo" extension, it would be better to support those subsets.
2025-04-16 00:56:48 +00:00
Tsukasa OI
53e89494b3 RISC-V: Use target_arch for RV(32|64) detection
As Taiki Endo pointed out, there's a problem if we continue using
`target_pointer_width` values to detect an architecture because:

*   There are separate `target_arch`s already and
*   There is an experimental ABI (not ratified though): RV64ILP32.
    cf. <https://lpc.events/event/17/contributions/1475/attachments/1186/2442/rv64ilp32_%20Run%20ILP32%20on%20RV64%20ISA.pdf>

Co-Authored-By: Taiki Endo <te316e89@gmail.com>
2025-04-16 00:56:48 +00:00
Tsukasa OI
2759545fda RISC-V: Remove enable_features
This commit prepares common infrastructure for extension implication by
removing `enable_features` closure which makes each feature test longer
(because it needs extra `value` argument each time we test a feature).

It comes with the overhead to enable each feature separately but later
mitigated by the OS-independent extension implication logic.
2025-04-16 00:56:48 +00:00