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This commit is contained in:
Bing Wen 2024-11-27 12:23:13 +08:00
parent 8eaa3c8fd3
commit 52ab015fac
6 changed files with 66 additions and 88 deletions
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19
embassy-stm32/src/fmt.rs
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@ -6,6 +6,25 @@ use core::fmt::{Debug, Display, LowerHex};
#[cfg(all(feature = "defmt", feature = "log"))] #[cfg(all(feature = "defmt", feature = "log"))]
compile_error!("You may not enable both `defmt` and `log` features."); compile_error!("You may not enable both `defmt` and `log` features.");
#[collapse_debuginfo(yes)]
macro_rules! rcc_assert {
($($x:tt)*) => {
{
if cfg!(feature = "unchecked-overclocking") {
#[cfg(not(feature = "defmt"))]
::core::assert!($($x)*);
#[cfg(feature = "defmt")]
::defmt::assert!($($x)*);
} else {
#[cfg(feature = "log")]
::log::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled.");
#[cfg(feature = "defmt")]
::defmt::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled.");
}
}
};
}
#[collapse_debuginfo(yes)] #[collapse_debuginfo(yes)]
macro_rules! assert { macro_rules! assert {
($($x:tt)*) => { ($($x:tt)*) => {

18
embassy-stm32/src/rcc/c0.rs
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@ -109,12 +109,9 @@ pub(crate) unsafe fn init(config: Config) {
None None
} }
Some(hse) => { Some(hse) => {
#[cfg(not(feature = "unchecked-overclocking"))] match hse.mode {
{ HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
match hse.mode { HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
} }
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -129,17 +126,14 @@ pub(crate) unsafe fn init(config: Config) {
Sysclk::HSE => unwrap!(hse), Sysclk::HSE => unwrap!(hse),
_ => unreachable!(), _ => unreachable!(),
}; };
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::SYSCLK.contains(&sys));
assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency. // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre; let hclk = sys / config.ahb_pre;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::HCLK.contains(&hclk));
assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre); let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert(max::PCLK.contains(&pclk1));
assert!(max::PCLK.contains(&pclk1));
let latency = match hclk.0 { let latency = match hclk.0 {
..=24_000_000 => Latency::WS0, ..=24_000_000 => Latency::WS0,

29
embassy-stm32/src/rcc/f013.rs
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@ -157,12 +157,9 @@ pub(crate) unsafe fn init(config: Config) {
None None
} }
Some(hse) => { Some(hse) => {
#[cfg(not(feature = "unchecked-overclocking"))] match hse.mode {
{ HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
match hse.mode { HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
} }
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -195,11 +192,9 @@ pub(crate) unsafe fn init(config: Config) {
PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)), PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
}; };
let in_freq = src_freq / pll.prediv; let in_freq = src_freq / pll.prediv;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_IN.contains(&in_freq));
assert!(max::PLL_IN.contains(&in_freq));
#[cfg(not(feature = "unchecked-overclocking"))]
let out_freq = in_freq * pll.mul; let out_freq = in_freq * pll.mul;
assert!(max::PLL_OUT.contains(&out_freq)); rcc_assert!(max::PLL_OUT.contains(&out_freq));
#[cfg(not(stm32f1))] #[cfg(not(stm32f1))]
RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv)); RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
@ -243,17 +238,15 @@ pub(crate) unsafe fn init(config: Config) {
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre); let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
#[cfg(stm32f0)] #[cfg(stm32f0)]
let (pclk2, pclk2_tim) = (pclk1, pclk1_tim); let (pclk2, pclk2_tim) = (pclk1, pclk1_tim);
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::HCLK.contains(&hclk));
assert!(max::HCLK.contains(&hclk)); rcc_assert!(max::PCLK1.contains(&pclk1));
#[cfg(not(feature = "unchecked-overclocking"))] #[cfg(not(stm32f0))]
assert!(max::PCLK1.contains(&pclk1)); rcc_assert!(max::PCLK2.contains(&pclk2));
#[cfg(all(not(feature = "unchecked-overclocking"), not(stm32f0)))]
assert!(max::PCLK2.contains(&pclk2));
#[cfg(stm32f1)] #[cfg(stm32f1)]
let adc = pclk2 / config.adc_pre; let adc = pclk2 / config.adc_pre;
#[cfg(all(not(feature = "unchecked-overclocking"), stm32f1))] #[cfg(stm32f1)]
assert!(max::ADC.contains(&adc)); rcc_assert!(max::ADC.contains(&adc));
// Set latency based on HCLK frquency // Set latency based on HCLK frquency
#[cfg(stm32f0)] #[cfg(stm32f0)]

22
embassy-stm32/src/rcc/f247.rs
View File

@ -169,12 +169,9 @@ pub(crate) unsafe fn init(config: Config) {
None None
} }
Some(hse) => { Some(hse) => {
#[cfg(not(feature = "unchecked-overclocking"))] match hse.mode {
{ HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
match hse.mode { HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
} }
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -207,14 +204,11 @@ pub(crate) unsafe fn init(config: Config) {
let hclk = sys / config.ahb_pre; let hclk = sys / config.ahb_pre;
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre); let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre); let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::SYSCLK.contains(&sys)); rcc_assert!(max::SYSCLK.contains(&sys));
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::HCLK.contains(&hclk));
assert!(max::HCLK.contains(&hclk)); rcc_assert!(max::PCLK1.contains(&pclk1));
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PCLK2.contains(&pclk2));
assert!(max::PCLK1.contains(&pclk1));
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PCLK2.contains(&pclk2));
let rtc = config.ls.init(); let rtc = config.ls.init();

33
embassy-stm32/src/rcc/g0.rs
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@ -139,12 +139,9 @@ pub(crate) unsafe fn init(config: Config) {
None None
} }
Some(hse) => { Some(hse) => {
#[cfg(not(feature = "unchecked-overclocking"))] match hse.mode {
{ HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
match hse.mode { HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
} }
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -172,11 +169,9 @@ pub(crate) unsafe fn init(config: Config) {
while RCC.cr().read().pllrdy() {} while RCC.cr().read().pllrdy() {}
let in_freq = src_freq / pll_config.prediv; let in_freq = src_freq / pll_config.prediv;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_IN.contains(&in_freq));
assert!(max::PLL_IN.contains(&in_freq));
let internal_freq = in_freq * pll_config.mul; let internal_freq = in_freq * pll_config.mul;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_VCO.contains(&internal_freq));
assert!(max::PLL_VCO.contains(&internal_freq));
RCC.pllcfgr().write(|w| { RCC.pllcfgr().write(|w| {
w.set_plln(pll_config.mul); w.set_plln(pll_config.mul);
@ -190,8 +185,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllpen(true); w.set_pllpen(true);
}); });
let freq = internal_freq / div_p; let freq = internal_freq / div_p;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_P.contains(&freq));
assert!(max::PLL_P.contains(&freq));
freq freq
}); });
@ -201,8 +195,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllqen(true); w.set_pllqen(true);
}); });
let freq = internal_freq / div_q; let freq = internal_freq / div_q;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_Q.contains(&freq));
assert!(max::PLL_Q.contains(&freq));
freq freq
}); });
@ -212,8 +205,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllren(true); w.set_pllren(true);
}); });
let freq = internal_freq / div_r; let freq = internal_freq / div_r;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_R.contains(&freq));
assert!(max::PLL_R.contains(&freq));
freq freq
}); });
@ -235,17 +227,14 @@ pub(crate) unsafe fn init(config: Config) {
Sysclk::PLL1_R => unwrap!(pll.pll_r), Sysclk::PLL1_R => unwrap!(pll.pll_r),
_ => unreachable!(), _ => unreachable!(),
}; };
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::SYSCLK.contains(&sys));
assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency. // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre; let hclk = sys / config.ahb_pre;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::HCLK.contains(&hclk));
assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre); let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PCLK.contains(&pclk1));
assert!(max::PCLK.contains(&pclk1));
let latency = match (config.voltage_range, hclk.0) { let latency = match (config.voltage_range, hclk.0) {
(VoltageRange::RANGE1, ..=24_000_000) => Latency::WS0, (VoltageRange::RANGE1, ..=24_000_000) => Latency::WS0,

33
embassy-stm32/src/rcc/g4.rs
View File

@ -140,12 +140,9 @@ pub(crate) unsafe fn init(config: Config) {
None None
} }
Some(hse) => { Some(hse) => {
#[cfg(not(feature = "unchecked-overclocking"))] match hse.mode {
{ HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
match hse.mode { HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
} }
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -172,12 +169,10 @@ pub(crate) unsafe fn init(config: Config) {
while RCC.cr().read().pllrdy() {} while RCC.cr().read().pllrdy() {}
let in_freq = src_freq / pll_config.prediv; let in_freq = src_freq / pll_config.prediv;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_IN.contains(&in_freq));
assert!(max::PLL_IN.contains(&in_freq));
let internal_freq = in_freq * pll_config.mul; let internal_freq = in_freq * pll_config.mul;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_VCO.contains(&internal_freq));
assert!(max::PLL_VCO.contains(&internal_freq));
RCC.pllcfgr().write(|w| { RCC.pllcfgr().write(|w| {
w.set_plln(pll_config.mul); w.set_plln(pll_config.mul);
@ -191,8 +186,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllpen(true); w.set_pllpen(true);
}); });
let freq = internal_freq / div_p; let freq = internal_freq / div_p;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_P.contains(&freq));
assert!(max::PLL_P.contains(&freq));
freq freq
}); });
@ -202,8 +196,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllqen(true); w.set_pllqen(true);
}); });
let freq = internal_freq / div_q; let freq = internal_freq / div_q;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_Q.contains(&freq));
assert!(max::PLL_Q.contains(&freq));
freq freq
}); });
@ -213,8 +206,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllren(true); w.set_pllren(true);
}); });
let freq = internal_freq / div_r; let freq = internal_freq / div_r;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PLL_R.contains(&freq));
assert!(max::PLL_R.contains(&freq));
freq freq
}); });
@ -237,18 +229,15 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(), _ => unreachable!(),
}; };
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::SYSCLK.contains(&sys));
assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency. // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre; let hclk = sys / config.ahb_pre;
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::HCLK.contains(&hclk));
assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre); let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre); let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
#[cfg(not(feature = "unchecked-overclocking"))] rcc_assert!(max::PCLK.contains(&pclk2));
assert!(max::PCLK.contains(&pclk2));
// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!) // Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
if config.boost { if config.boost {