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Merge #398

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398: Extract SPI exclusive device into shared crate r=Dirbaio a=eldruin

Some concerns have been raised regarding the error handling in `spi::blocking::ExclusiveDevice`.
I am not sure what the problem was, though.
I think `@GrantM11235` was the one to raise the concerns so maybe he can elaborate and then I can improve this description.
Since that struct is just a helpful wrapper for a very specific situation, I propose we move it out of `embedded-hal` itself. For example into an `embedded-hal-shared` crate (or some other name, feel free to bikeshed).

We should note that we (probably) have the same problem in `embedded-hal-async` where there is also an `ExclusiveDevice` for SPI, so if we create such a crate, we should agree on what to put in there:
1. Only blocking `ExclusiveDevice`
2. blocking + async `ExclusiveDevice`
3. any of the above + `RefCell`-based sharing
4. any of the above + some mutex / critical section

We should also note that the great `shared-bus` crate also solves some of these problems so we might also put (some?) of this there.

cc: `@Rahix`

Co-authored-by: Diego Barrios Romero <eldruin@gmail.com>
This commit is contained in:
bors[bot]
2022-08-17 14:19:00 +00:00
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CHANGELOG.md
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@@ -15,6 +15,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
### Removed
- `digital::blocking::IoPin` traits.
- `spi::blocking::ExclusiveDevice` and `spi::blocking::ExclusiveDeviceError`. These have been moved to a separate crate.
## [v1.0.0-alpha.8] - 2022-04-15

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# Change Log
All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/)
and this project adheres to [Semantic Versioning](http://semver.org/).
## [Unreleased]

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[package]
authors = [
"The Embedded HAL Team and Contributors <embedded-hal@teams.rust-embedded.org>",
]
categories = ["embedded", "hardware-support", "no-std"]
description = "Bus/Device connection mechanisms for embedded-hal, a Hardware Abstraction Layer (HAL) for embedded systems"
documentation = "https://docs.rs/embedded-hal-bus"
edition = "2018"
keywords = ["hal", "IO"]
license = "MIT OR Apache-2.0"
name = "embedded-hal-bus"
readme = "README.md"
repository = "https://github.com/rust-embedded/embedded-hal"
version = "0.1.0-alpha.1"
[dependencies]
embedded-hal = { version = "=1.0.0-alpha.8", path = ".." }

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Copyright (c) 2021-2022 The Rust embedded HAL team and contributors.
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SOFTWARE.

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[![crates.io](https://img.shields.io/crates/d/embedded-hal-bus.svg)](https://crates.io/crates/embedded-hal-bus)
[![crates.io](https://img.shields.io/crates/v/embedded-hal-bus.svg)](https://crates.io/crates/embedded-hal-bus)
[![Documentation](https://docs.rs/embedded-hal-bus/badge.svg)](https://docs.rs/embedded-hal-bus)
<!--
![Minimum Supported Rust Version](https://img.shields.io/badge/rustc-1.54+-blue.svg)
-->
# `embedded-hal-bus`
Bus/Device connection mechanisms for [`embedded-hal`], a Hardware Abstraction Layer (HAL) for embedded systems.
It is possible to connect several peripherals to a bus like SPI or I2C.
To support this, `embedded-hal` provides the `SpiBus` and `SpiDevice` traits in the case of SPI, for example.
`embedded-hal` trait implementations for microcontrollers should implement the `...Bus` traits.
However, device drivers should use the `...Device` traits, _not the `...Bus` traits_ if at all possible
in order to allow for sharing of the bus they are connected to.
This crate provides mechanisms to connect a `...Bus` and a `...Device`.
For further details on these traits, please consult the [`embedded-hal` documentation](https://docs.rs/embedded-hal).
This project is developed and maintained by the [HAL team][team].
## [API reference]
[API reference]: https://docs.rs/embedded-hal-bus
<!--
## Minimum Supported Rust Version (MSRV)
This crate is guaranteed to compile on stable Rust 1.54 and up. It *might*
compile with older versions but that may change in any new patch release.
-->
## License
Licensed under either of
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
http://www.apache.org/licenses/LICENSE-2.0)
- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
at your option.
### Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
dual licensed as above, without any additional terms or conditions.
## Code of Conduct
Contribution to this crate is organized under the terms of the [Rust Code of
Conduct][CoC], the maintainer of this crate, the [HAL team][team], promises
to intervene to uphold that code of conduct.
[CoC]: ../CODE_OF_CONDUCT.md
[team]: https://github.com/rust-embedded/wg#the-hal-team
[`embedded-hal`]: https://crates.io/crates/embedded-hal

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//! Bus/Device connection mechanisms for [`embedded-hal`], a Hardware Abstraction Layer (HAL) for embedded systems.
//!
//! It is possible to connect several peripherals to a bus like SPI or I2C.
//! To support this, `embedded-hal` provides the `SpiBus` and `SpiDevice` traits in the case of SPI, for example.
//!
//! `embedded-hal` trait implementations for microcontrollers should implement the `...Bus` traits.
//! However, device drivers should use the `...Device` traits, _not the `...Bus` traits_ if at all possible
//! in order to allow for sharing of the bus they are connected to.
//!
//! This crate provides mechanisms to connect a `...Bus` and a `...Device`.
//!
//! For further details on these traits, please consult the [`embedded-hal` documentation](https://docs.rs/embedded-hal).
#![warn(missing_docs)]
#![no_std]
pub mod spi;

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//! SPI bus sharing mechanisms.
/// SPI bus sharing with blocking traits
pub mod blocking {
use core::fmt::Debug;
use embedded_hal::{
digital::blocking::OutputPin,
spi::{
blocking::{SpiBusFlush, SpiDevice},
Error, ErrorKind, ErrorType,
},
};
/// Error type for [`ExclusiveDevice`] operations.
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub enum ExclusiveDeviceError<BUS, CS> {
/// An inner SPI bus operation failed
Spi(BUS),
/// Asserting or deasserting CS failed
Cs(CS),
}
impl<BUS, CS> Error for ExclusiveDeviceError<BUS, CS>
where
BUS: Error + Debug,
CS: Debug,
{
fn kind(&self) -> ErrorKind {
match self {
Self::Spi(e) => e.kind(),
Self::Cs(_) => ErrorKind::ChipSelectFault,
}
}
}
/// [`SpiDevice`] implementation with exclusive access to the bus (not shared).
///
/// This is the most straightforward way of obtaining an [`SpiDevice`] from an [`SpiBus`],
/// ideal for when no sharing is required (only one SPI device is present on the bus).
pub struct ExclusiveDevice<BUS, CS> {
bus: BUS,
cs: CS,
}
impl<BUS, CS> ExclusiveDevice<BUS, CS> {
/// Create a new ExclusiveDevice
pub fn new(bus: BUS, cs: CS) -> Self {
Self { bus, cs }
}
}
impl<BUS, CS> ErrorType for ExclusiveDevice<BUS, CS>
where
BUS: ErrorType,
CS: OutputPin,
{
type Error = ExclusiveDeviceError<BUS::Error, CS::Error>;
}
impl<BUS, CS> SpiDevice for ExclusiveDevice<BUS, CS>
where
BUS: SpiBusFlush,
CS: OutputPin,
{
type Bus = BUS;
fn transaction<R>(
&mut self,
f: impl FnOnce(&mut Self::Bus) -> Result<R, <Self::Bus as ErrorType>::Error>,
) -> Result<R, Self::Error> {
self.cs.set_low().map_err(ExclusiveDeviceError::Cs)?;
let f_res = f(&mut self.bus);
// On failure, it's important to still flush and deassert CS.
let flush_res = self.bus.flush();
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(ExclusiveDeviceError::Spi)?;
flush_res.map_err(ExclusiveDeviceError::Spi)?;
cs_res.map_err(ExclusiveDeviceError::Cs)?;
Ok(f_res)
}
}
}

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@@ -167,11 +167,7 @@
//! for them to return before the bus is idle. For example, assuming SPI mode 0, the last bit is sampled on the first (rising) edge
//! of SCK, at which point a method could return, but the second (falling) SCK edge still has to happen before the bus is idle.
use core::fmt::Debug;
use crate::{digital::blocking::OutputPin, spi::ErrorType};
use super::{Error, ErrorKind};
use crate::spi::ErrorType;
/// SPI device trait
///
@@ -350,76 +346,3 @@ impl<T: SpiBus<Word>, Word: Copy> SpiBus<Word> for &mut T {
T::transfer_in_place(self, words)
}
}
/// Error type for [`ExclusiveDevice`] operations.
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub enum ExclusiveDeviceError<BUS, CS> {
/// An inner SPI bus operation failed
Spi(BUS),
/// Asserting or deasserting CS failed
Cs(CS),
}
impl<BUS, CS> Error for ExclusiveDeviceError<BUS, CS>
where
BUS: Error + Debug,
CS: Debug,
{
fn kind(&self) -> ErrorKind {
match self {
Self::Spi(e) => e.kind(),
Self::Cs(_) => ErrorKind::ChipSelectFault,
}
}
}
/// [`SpiDevice`] implementation with exclusive access to the bus (not shared).
///
/// This is the most straightforward way of obtaining an [`SpiDevice`] from an [`SpiBus`],
/// ideal for when no sharing is required (only one SPI device is present on the bus).
pub struct ExclusiveDevice<BUS, CS> {
bus: BUS,
cs: CS,
}
impl<BUS, CS> ExclusiveDevice<BUS, CS> {
/// Create a new ExclusiveDevice
pub fn new(bus: BUS, cs: CS) -> Self {
Self { bus, cs }
}
}
impl<BUS, CS> ErrorType for ExclusiveDevice<BUS, CS>
where
BUS: ErrorType,
CS: OutputPin,
{
type Error = ExclusiveDeviceError<BUS::Error, CS::Error>;
}
impl<BUS, CS> SpiDevice for ExclusiveDevice<BUS, CS>
where
BUS: SpiBusFlush,
CS: OutputPin,
{
type Bus = BUS;
fn transaction<R>(
&mut self,
f: impl FnOnce(&mut Self::Bus) -> Result<R, <Self::Bus as ErrorType>::Error>,
) -> Result<R, Self::Error> {
self.cs.set_low().map_err(ExclusiveDeviceError::Cs)?;
let f_res = f(&mut self.bus);
// On failure, it's important to still flush and deassert CS.
let flush_res = self.bus.flush();
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(ExclusiveDeviceError::Spi)?;
flush_res.map_err(ExclusiveDeviceError::Spi)?;
cs_res.map_err(ExclusiveDeviceError::Cs)?;
Ok(f_res)
}
}