* make pins optional for Spi::new (master, full-duplex mode)
* add additional method to setup spi pins (master, full-duplex mode)
* add additional method to setup spi pins (master, half-duplex mode)
* remove generic type parameters for Spi::new
* update documentation
* make `with_pins` could be chained
* update CHANGELOG.md
* update CHANGELOG.md
* make the return value of a method like `with_{*}` owned
* fix (maybe?) all broken examples caused by the change (esp32-hal)
* fix (maybe?) all broken examples caused by the change (esp32c2-hal)
* fix (maybe?) all broken examples caused by the change (esp32c3-hal)
* fix (maybe?) all broken examples caused by the change (esp32c6-hal)
* fix (maybe?) all broken examples caused by the change (esp32h2-hal)
* fix (maybe?) all broken examples caused by the change (esp32s2-hal)
* fix (maybe?) all broken examples caused by the change (esp32s3-hal)
* rerun 'cargo fmt' for esp-hal-common
* rerun 'cargo fmt' for the rest of examples
* Temporarily disable async `SYSTIMER` implementation, remove mention from `CHANGELOG.md`
* Remove a couple files which are not required
* Fix warning for `sha` examples
* Fix warning for non-C3 devices
* s/interrupt_clear/clear_interrupt/
* Provide ADC values in mV instead of requiring the user to scale them
* Changelog
* Try converting poly calibration also
* Update changelog and comments
* Fix example
* Force frame pointers for RISC-V chips
* Various dependency updates
* Update to latest published PACs and resolve build errors
* Top-level `README` updates
* Further clarify when `RUSCT_BOOTSTRAP=1` is required
* Fix Async UART
The uart handler was `writing` to the enable register instead of
`modify`, which meant any wake would see the cleared enabled bit and
think the event had occurred. This wasn't seen before the split of uart
because it was only possible to listen to one thing at a time.
This PR also removes the ReadBufferFull error in favour of returning the
max bytes in the buffer.
The serial examples has been updated to actually have some cross task
communication.
* changelog
* fix dev deps
* Move SPI-related traits into their own preludes in the `spi` module
* Remove the `embedded-hal-async` trait re-exports and the `eh1` module from the prelude
* Update `CHANGELOG.md`
* Remove duplicated `analog` modules, which are not necessary
* Merge the `SarAdcExt` and `SensExt` traits into a single `AnalogExt` trait
* Clean up/simplify the analog module a bit
* Update `CHANGELOG.md`
* Refactor the `spi` and `spi_slave` modules into a single `spi` module
* Update import paths in examples as needed
* Extract some common types from `spi::master` into the root `spi` module
* Fix imports in examples (again)
* Documentation fixes/improvements
* Remove unnecessary re-exports
* Update `CHANGELOG.md`
* Duplicate spi to spi_slave
* Restore spi
* Add barebones SPI slave mode, DMA only.
This setup allows registering buffers for future transactions the master
does (lowering cs, toggling sclk, and raising cs again). The transfer
struct returned from the registration API will complete its wait() or
return true from is_done() after cs has been raised.
Copied from spi.rs, so most of the changes are deleting code that
handles e.g. segmented transfers or synchronous operations.
Fix non-c3 devices' builds
* Limit spi_slave to non-pdma devices
* SPI slave DMA example
Ensure the API "feels" right.
Since there's no way to route GPIOs to other peripherals, we choose four
other wires and bit-bang SPI for the master side, relying on the person
running the example to connect the bus. This way we ensure the slave
code works, since we created the master ourselves.
Also, it's not really possible to use a second ESP device as the master
anyway: all the digital lines have glitches on startup, and those
glitches cause the slave's DMA engine to skip descriptors (it thinks
they're intended CS indicators); this causes it to lose data.
Then, fix the bitbang master (recording the progression here)
- When bitbanging, iterate the bits by "for _ in 0..8", instead of the
broken "for _ in [0..8]". The latter only runs the iteration once,
since there's only one list given ... and because the code uses _
instead of a real loop variable, type checking didn't save us.
- When bitbanging, send the bits out (and read them in) MSB first, since
that's actually how we have the slave configured.
* Add changelog entry
* Split DMA prepare_transfer into two fns.
The first does everything but write to the start bit and check for an
error. The second does those. We need 2 fns because the SPI slave needs
to start the transfer only after resetting the various afifo hardware
components (if it starts the transfer before, the first 8 bytes will be
lost when that reset happens).
Use the split fns everywhere.
Also split flush(). It needs to be pollable, so split it into one fn that
polls and one that waits until the poll returns clear. Also call the poll
fn from the is_done() fn, so we don't trample in-progress transfers.
* Make example code fill rx buffer before transfer
This way we can tell if it's ever touching certain bytes - 0xff is never
added to the master transmit buffer.
While I'm changing this, make the slave tx buffer never contain 0xff
either (go from 254 to 0).
---------
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Make sure examples can build with defmt
* Remove duplicate example checks
* Fix examples
* Add changelog entry
* Actually build some examples with defmt feature enabled
* Add the defmt linker script in each package's build script
