* CS impl
* use CS Mutex in C3 examples
* use CS Mutex in S2 examples
* Update esp32 example
* run fmt
* Update S3 examples
* Remove uses of unsafe where no longer required
* use esp_backtrace in examples
* fix import & fmt once more
* Bump MSRV to 1.60.0
Co-authored-by: Jesse Braham <jesse@beta7.io>
In 7b59c9e76d
linker scripts have been moved in the ld/ sub-folder for every target.
The change detection path in build.rs of every target hasn't been updated, resulting in
the build script running at every code change, rather than only when there's a change in memory.x
* common/spi: Turn fifo size into const
instead of hard-coding it into the code in various places.
* common/spi: Alias `write_bytes` to `send_bytes`
since they share the same interface and the same code anyway.
* common/spi: Implement `read_bytes`
as counterpart to `send_bytes` that is responsible only for reading
bytes received via SPI.
* common/spi: Rewrite `transfer`
to use `send_bytes` and `read_bytes` under the hood and remove duplicate
code.
* common/spi: Create submodule for embedded_hal_1
that is re-exported when the `eh1` feature flag is active. This removes
lots of duplicate `#[cfg(...)]` macros previously part of the code.
* common/spi: Implement `SpiBus` and `SpiBusWrite`
traits from the `embedded-hal 1.0.0-alpha.8`.
* common/spi: Make `mosi` pin optional
* esp32-hal: Add new SPI example with `eh1` traits
* esp32-hal/examples/spi_eh1: Add huge transfer
and bump the SPI speed to 1 MHz.
* common/spi: Apply rustfmt
* common/spi: Use `memcpy` to read from registers
This cuts down the time between consecutive transfers from about 2 ms
to less than 1 ms.
* WIP: common/spi: Use `ptr::copy` to fill write FIFO
cutting down the time between transfers from just below 1 ms to ~370 us.
The implementation is currently broken in that it will always fill the
entire FIFO from the input it is given, even if that isn't FIFO-sized...
* common/spi: Add more documentation
* esp32/examples/spi_eh1: Fix `transfer_in_place`
* esp32/examples/spi_eh1: Add conditional compile
and compile a dummy instead when the "eh1" feature isn't present.
* esp32-hal: Ignore spi_eh1 example
in normal builds, where the feature flag "eh1" isn't given. Building the
example directly via `cargo build --example spi_eh1_loopback` will now
print an error that this requires a feature flag to be active.
* common/spi: Use `write_bytes`
and drop `send_bytes` instead. Previoulsy, both served the same purpose,
but `send_bytes` was introduced more recently and is hence less likely
to cause breaking changes in existing code.
* common/spi: Fix mosi pin setup
* Add SPI examples with ehal 1.0.0-alpha8 traits
to all targets.
* common/spi: Fix `read` behavior
The previous `read` implementation would only read the contents of the
SPI receive FIFO and return that as data. However, the `SpiBusRead`
trait defines that while reading, bytes should be written out to the bus
(Because SPI is transactional, without writing nothing can be read).
Reimplements the `embedded-hal` traits to correctly implement this
behavior.
* common/spi: Use full FIFO size on all variants
All esp variants except for the esp32s2 have a 64 byte FIFO, whereas the
esp32s2 has a 72 byte FIFO.
* common/spi: Use common pad byte for empty writes
* common/spi: Fix reading bytes from FIFO
by reverting to the old method of reading 32 bytes at a time and
assembling the return buffer from that. It turns out that the previous
`core::slice::from_raw_parts()` doesn't work for the esp32s2 and esp32s3
variants, returning bogus data even though the correct data is present
in the registers.
* common/spi: Fix typos
* examples: Fix spi_eh1_loopback examples
* common/gpio: Allow disconnecting IO from peripheral
* common/gpio: Allow disconnecting input from peripheral
* common/gpio: Document functions for disconnecting
IOs from peripherals.
* common/gpio: Use generic alternate function
passed in from the gpio configuration.
If bss contained anything a linker error was emitted about overlapping
sections. Moving the .bss section to after the .rwtext, and adding a dummy
section to pad data bus access to the bss section fixes this.
* esp32: Fix typo in Frequency word in some identifiers
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add support for PLL clock configuration
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* clock: Move definition of Clock types to common level
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add support for RTC Clock configuration
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add example for the RTC Watchdog Timer driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Instead of building a table of _all_ configured interrupts,
we now only check the currently _pending_ interrupts configuration
status. This means in the best case scenario we only ever do _one_
lookup instead of the 60~ we did before.
Tested on esp32c3, gpio_interrupt:
Before: 850cycles from `handler_interrupts` to the actual handler
After: 125cycles
* RISCV interrupt vectoring
- Adds support for vectoring peripheral interrupts to PAC handlers
- Currently supports level interrupts with priorities from 1-15
- Updated the gpio interrupt example to reflect the new changes
* remove .vscode files
* Support vectored edge interrupts
This is as simple as making sure we clear the CPU interrupt whenever we
receive one. This also documents further what APIs are safe to call when
the `vectored` feature is enabled.
* fix all examples to use vectoring
* doc & cleanup
* run handlers from ram
* make xtensa::interrupt::vectored private, we rexport public items
* fix default handlers
* pass interrupt into EspDefaultHandler
* Xtensa interrupt vectoring: peripheral source
- Initial Xtensa vectoring, updated esp32 gpio example to use new interrupt macro.
- Only peripheral sources supported.
- Only level one priority supported.
- CPU & Edge interrupts still need to be handled.
* Xtensa interrupt vectoring: CPU & EDGE
- Add support for handling CPU interrupts and edge interrupts
- PR required to xtensa-lx-rt for CPU handlers
* Xtensa interrupt vectoring: Priority
- Finally implement priortization
- Only three priorities available at the moment. Xtensa programmer guide
discourages using highpri interrupts in Rust/C. Guide also mentions
using software priortization to increase the number of Priorities
available
* support CPU interrupts, using patch xtensa-lx-rt
* Update example
* Add support & examples for the s2 & s3 too
* Fix formatting and missing imports
* Run interrupt handling in ram, optionally run the vector handler in ram in the examples
* Use xtensa_lx::Mutex CS when enabling interrupts
* Run clippy on each target
* Remove redundant features
* Fix C3 builds
* make enable unsafe. Add note about preallocated interrupts in vectored mode.
* Remove `INTERRUPT_LEVELS` static
The interrupt levels static introduces a few issues
- A lock is needed when configuring interrupts to keep
INTERRUPT_LEVELS in a consistent state
- Interrupts enabled from outside the Rust domain wouldn't be
serviced, this is the case with the wifi blobs
To remove it, the prioty configuration is now calculated dynamically in
the interrupt handler. Essentially INTERRUPT_LEVELS is now created once
the interrupt triggers. It has some benefits, such as only having to
look at interrupts configured on the current core, not both, but there
is of course an overhead with doing this in the interrupt.
* Allow raw interrupts on levels 4-7, whilst also supporting vectoring on levels 1-3
* rename core number features
* Fix examples and formatting
* use xtensa-lx-rt release, update pacs
* Support passing the trap frame into interrupt handlers
* cfg away the #[interrupt] macro when not using vectoring
* rename enable to map
move vectored feature to chip specific hals
* export vectored functions
- rename `enable_with_priority` to `enable`
- add docs for interrupt macro
* Update all examples to use vectored interrupts
