9 Commits

Author SHA1 Message Date
Scott Mabin
be184a552d
critical_section implementations & esp_backtrace (#151)
* CS impl

* use CS Mutex in C3 examples

* use CS Mutex in S2 examples

* Update esp32 example

* run fmt

* Update S3 examples

* Remove uses of unsafe where no longer required

* use esp_backtrace in examples

* fix import & fmt once more

* Bump MSRV to 1.60.0

Co-authored-by: Jesse Braham <jesse@beta7.io>
2022-08-22 20:02:28 +01:00
Scott Mabin
1789780d06
Xtensa vectored interrupts (#103)
* Xtensa interrupt vectoring: peripheral source

- Initial Xtensa vectoring, updated esp32 gpio example to use new interrupt macro.
- Only peripheral sources supported.
- Only level one priority supported.
- CPU & Edge interrupts still need to be handled.

* Xtensa interrupt vectoring: CPU & EDGE

- Add support for handling CPU interrupts and edge interrupts
- PR required to xtensa-lx-rt for CPU handlers

* Xtensa interrupt vectoring: Priority

- Finally implement priortization
- Only three priorities available at the moment. Xtensa programmer guide
  discourages using highpri interrupts in Rust/C. Guide also mentions
  using software priortization to increase the number of Priorities
  available

* support CPU interrupts, using patch xtensa-lx-rt

* Update example

* Add support & examples for the s2 & s3 too

* Fix formatting and missing imports

* Run interrupt handling in ram, optionally run the vector handler in ram in the examples

* Use xtensa_lx::Mutex CS when enabling interrupts

* Run clippy on each target

* Remove redundant features

* Fix C3 builds

* make enable unsafe. Add note about preallocated interrupts in vectored mode.

* Remove `INTERRUPT_LEVELS` static

The interrupt levels static introduces a few issues
  - A lock is needed when configuring interrupts to keep
    INTERRUPT_LEVELS in a consistent state
  - Interrupts enabled from outside the Rust domain wouldn't be
    serviced, this is the case with the wifi blobs

To remove it, the prioty configuration is now calculated dynamically in
the interrupt handler. Essentially INTERRUPT_LEVELS is now created once
the interrupt triggers. It has some benefits, such as only having to
look at interrupts configured on the current core, not both, but there
is of course an overhead with doing this in the interrupt.

* Allow raw interrupts on levels 4-7, whilst also supporting vectoring on levels 1-3

* rename core number features

* Fix examples and formatting

* use xtensa-lx-rt release, update pacs

* Support passing the trap frame into interrupt handlers

* cfg away the #[interrupt] macro when not using vectoring

* rename enable to map

move vectored feature to chip specific hals

* export vectored functions

- rename `enable_with_priority` to `enable`
- add docs for interrupt macro

* Update all examples to use vectored interrupts
2022-07-25 07:12:34 -07:00
bjoernQ
70a9437f27 Add more documentation to the examples 2022-07-22 11:41:58 +02:00
Björn Quentin
147d8de988
Separate TIMG into timer0, (timer1), wdt (#104)
* Separate TIMG into timer0, (timer1), wdt
* Apply suggestions from code review
* Remove left-over code
* Ignore settings.json
2022-07-20 06:51:39 -07:00
Björn Quentin
e612bd1120
Add some config options to the UART driver (#99)
* Add some config options to the UART driver
* Use esp-println 0.2.0
* Remove the NoPin type
* Serial constructor now doesn't return a Result anymore
2022-07-12 08:00:02 -07:00
Jesse Braham
178a05522d Update all examples to reflect changes to Timer API 2022-06-29 17:57:23 -07:00
Robert Wiewel
dc59f7b777 Don't disable RWDT boot protection in RAM examples 2022-02-28 08:47:37 +01:00
Robert Wiewel
f2884bd3b8 Add RWDT disable in RTC_CNTL for ESP32/S2/S3 2022-02-25 23:41:05 +01:00
Björn Quentin
70109ffe36
Initial implementation of ram proc macro (#6)
* Add .iram section for ESP32C3, make it possible to use direct-boot or normal-boot

* Add ram proc-macro
2022-01-18 10:02:40 -08:00