* RISCV interrupt vectoring
- Adds support for vectoring peripheral interrupts to PAC handlers
- Currently supports level interrupts with priorities from 1-15
- Updated the gpio interrupt example to reflect the new changes
* remove .vscode files
* Support vectored edge interrupts
This is as simple as making sure we clear the CPU interrupt whenever we
receive one. This also documents further what APIs are safe to call when
the `vectored` feature is enabled.
* fix all examples to use vectoring
* doc & cleanup
* run handlers from ram
* make xtensa::interrupt::vectored private, we rexport public items
* fix default handlers
* pass interrupt into EspDefaultHandler
* initial systimer impl
* Add systimer example
* Make Alarms real singletons
* Remove runtime Option, turn into compile error
* Make Systimer::now() not take self
* refactor shared alarm methods
* Implement esp32c3 delay with monotonic SystemTimer::now()
* Add extend systimer support to esp32s3 and add example
* systimer: esp32s2 support
